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More tests in memlib/generate.py

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Covers most of the todo list, at least functionally.  Some minor issues with not always using hardware features.
This commit is contained in:
KrystalDelusion 2022-07-07 11:10:33 +12:00
parent af1b9c9e07
commit 7f033d3c1f
13 changed files with 1180 additions and 12 deletions
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61
tests/memlib/memlib_block_sp_full.txt Normal file
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ram block \RAM_BLOCK_SP {
cost 2;
abits 4;
width 16;
byte 8;
port srsw "A" {
clock posedge;
clken;
rden;
option "RDWR" "NO_CHANGE" {
rdwr no_change;
}
option "RDWR" "OLD" {
rdwr old;
}
option "RDWR" "NEW" {
rdwr new;
}
option "RDWR" "NEW_ONLY" {
rdwr new_only;
}
ifdef USE_ARST {
option "RDARST" "ZERO" {
rdarst zero;
}
option "RDARST" "ANY" {
rdarst any;
}
}
ifdef USE_SRST {
option "SRST_BLOCK" 0 {
option "SRST_GATE" 0 {
rdsrst zero ungated;
}
option "SRST_GATE" 1 {
rdsrst zero gated_clken;
}
option "SRST_GATE" 2 {
rdsrst zero gated_rden;
}
}
}
ifdef USE_SRST_BLOCKING {
option "SRST_BLOCK" 1 {
option "SRST_GATE" 0 {
rdsrst zero ungated block_wr;
}
option "SRST_GATE" 1 {
rdsrst zero gated_clken block_wr;
}
option "SRST_GATE" 2 {
rdsrst zero gated_rden block_wr;
}
}
}
}
}