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Add test cases for co-simulation

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Miodrag Milanovic 2022-02-02 13:22:44 +01:00
parent 4a30c9cb94
commit 7ef6da4c7d
7 changed files with 953 additions and 0 deletions
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read_verilog grom_computer.v grom_cpu.v alu.v ram_memory.v;
prep -top grom_computer;
sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -a -n 80
sim -clock clk -r grom.fst -scope grom_computer -start 25ns -stop 100ns -sim-cmp
sim -clock clk -r grom.fst -scope grom_computer -stop 100ns -sim-gold
sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate -a