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Added Verilog lexer and parser support for real values

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This commit is contained in:
Clifford Wolf 2014-06-13 11:29:23 +02:00
parent 482d9208aa
commit 7ef0da32cd
4 changed files with 31 additions and 3 deletions
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10
frontends/verilog/lexer.l
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@ -179,6 +179,16 @@ namespace VERILOG_FRONTEND {
return TOK_CONST;
}
[0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? {
frontend_verilog_yylval.string = new std::string(yytext);
return TOK_REAL;
}
[0-9][0-9_]*[eE][-+]?[0-9_]+ {
frontend_verilog_yylval.string = new std::string(yytext);
return TOK_REAL;
}
\" { BEGIN(STRING); }
<STRING>\\. { yymore(); }
<STRING>\" {