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Added Verilog lexer and parser support for real values

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This commit is contained in:
Clifford Wolf 2014-06-13 11:29:23 +02:00
parent 482d9208aa
commit 7ef0da32cd
4 changed files with 31 additions and 3 deletions
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5
frontends/ast/ast.cc
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@ -77,6 +77,7 @@ std::string AST::type2str(AstNodeType type)
X(AST_ARGUMENT)
X(AST_RANGE)
X(AST_CONSTANT)
X(AST_REALVALUE)
X(AST_CELLTYPE)
X(AST_IDENTIFIER)
X(AST_PREFIX)
@ -460,6 +461,10 @@ void AstNode::dumpVlog(FILE *f, std::string indent)
fprintf(f, "%zd'b %s", bits.size(), RTLIL::Const(bits).as_string().c_str());
break;
case AST_REALVALUE:
fprintf(f, "%e", realvalue);
break;
case AST_BLOCK:
if (children.size() == 1) {
children[0]->dumpVlog(f, indent);