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	dfflibmap: Refactor to use dfflegalize internally.
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					 5 changed files with 212 additions and 210 deletions
				
			
		
							
								
								
									
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								tests/techmap/dfflibmap-sim.v
									
										
									
									
									
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								tests/techmap/dfflibmap-sim.v
									
										
									
									
									
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module dffn(input CLK, D, output reg Q, output QN);
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always @(negedge CLK)
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	Q <= D;
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assign QN = ~Q;
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endmodule
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module dffsr(input CLK, D, CLEAR, PRESET, output reg Q, output QN);
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always @(posedge CLK, posedge CLEAR, posedge PRESET)
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	if (CLEAR)
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		Q <= 0;
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	else if (PRESET)
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		Q <= 1;
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	else
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		Q <= D;
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assign QN = ~Q;
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endmodule
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										55
									
								
								tests/techmap/dfflibmap.lib
									
										
									
									
									
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										55
									
								
								tests/techmap/dfflibmap.lib
									
										
									
									
									
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library(test) {
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  /* D-type flip-flop with asynchronous reset and preset */
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  cell (dffn) {
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    area : 6;
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    ff("IQ", "IQN") {
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      next_state : "D";
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      clocked_on : "!CLK";
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    } 
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    pin(D) {
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      direction : input;
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    }
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    pin(CLK) {
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      direction : input;
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    }
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    pin(Q) {
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      direction: output;
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      function : "IQ";
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    }
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    pin(QN) {
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      direction: output;
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      function : "IQN";
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    } 
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  }
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  cell (dffsr) {
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    area : 6;
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    ff("IQ", "IQN") {
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      next_state : "D";
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      clocked_on : "CLK";
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      clear      : "CLEAR";
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      preset     : "PRESET";
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      clear_preset_var1 : L;
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      clear_preset_var2 : L;
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    } 
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    pin(D) {
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      direction : input;
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    }
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    pin(CLK) {
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      direction : input;
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    }
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    pin(CLEAR) {
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      direction : input;
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    }
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    pin(PRESET) {
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      direction : input;
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    }
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    pin(Q) {
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      direction: output;
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      function : "IQ";
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    }
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    pin(QN) {
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      direction: output;
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      function : "IQN";
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    } 
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  }
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}
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										58
									
								
								tests/techmap/dfflibmap.ys
									
										
									
									
									
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										58
									
								
								tests/techmap/dfflibmap.ys
									
										
									
									
									
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read_verilog -icells <<EOT
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module top(input C, D, S, R, output [9:0] Q);
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$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
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$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
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$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
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$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
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$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(R), .S(S), .Q(Q[4]));
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assign Q[9:5] = ~Q[4:0];
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endmodule
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EOT
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simplemap
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design -save orig
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#equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -liberty dfflibmap.lib
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#equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -prepare -liberty dfflibmap.lib
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dfflibmap -prepare -liberty dfflibmap.lib
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equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -map-only -liberty dfflibmap.lib
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design -load orig
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dfflibmap -liberty dfflibmap.lib
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clean
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select -assert-count 4 t:$_NOT_
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select -assert-count 1 t:dffn
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select -assert-count 4 t:dffsr
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select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflibmap -prepare -liberty dfflibmap.lib
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select -assert-count 9 t:$_NOT_
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select -assert-count 1 t:$_DFF_N_
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select -assert-count 4 t:$_DFFSR_PPP_
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select -assert-none t:$_DFF_N_ t:$_DFFSR_PPP_ t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflibmap -map-only -liberty dfflibmap.lib
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select -assert-count 5 t:$_NOT_
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select -assert-count 0 t:dffn
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select -assert-count 1 t:dffsr
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design -load orig
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dfflibmap -prepare -liberty dfflibmap.lib
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dfflibmap -map-only -liberty dfflibmap.lib
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clean
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select -assert-count 4 t:$_NOT_
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select -assert-count 1 t:dffn
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select -assert-count 4 t:dffsr
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select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i
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