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dfflibmap: Refactor to use dfflegalize internally.

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This commit is contained in:
Marcelina Kościelnicka 2020-07-02 18:22:43 +02:00
parent 68babb2ae4
commit 7ed9d18907
5 changed files with 212 additions and 210 deletions
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2
tests/liberty/run-test.sh
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@ -5,6 +5,6 @@ for x in *.lib; do
echo "Running $x.."
echo "read_verilog small.v" > test.ys
echo "synth -top small" >> test.ys
echo "dfflibmap -liberty ${x}" >> test.ys
echo "dfflibmap -info -liberty ${x}" >> test.ys
../../yosys -ql ${x%.lib}.log -s test.ys
done

22
tests/techmap/dfflibmap-sim.v Normal file
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@ -0,0 +1,22 @@
module dffn(input CLK, D, output reg Q, output QN);
always @(negedge CLK)
Q <= D;
assign QN = ~Q;
endmodule
module dffsr(input CLK, D, CLEAR, PRESET, output reg Q, output QN);
always @(posedge CLK, posedge CLEAR, posedge PRESET)
if (CLEAR)
Q <= 0;
else if (PRESET)
Q <= 1;
else
Q <= D;
assign QN = ~Q;
endmodule

55
tests/techmap/dfflibmap.lib Normal file
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@ -0,0 +1,55 @@
library(test) {
/* D-type flip-flop with asynchronous reset and preset */
cell (dffn) {
area : 6;
ff("IQ", "IQN") {
next_state : "D";
clocked_on : "!CLK";
}
pin(D) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
}
pin(QN) {
direction: output;
function : "IQN";
}
}
cell (dffsr) {
area : 6;
ff("IQ", "IQN") {
next_state : "D";
clocked_on : "CLK";
clear : "CLEAR";
preset : "PRESET";
clear_preset_var1 : L;
clear_preset_var2 : L;
}
pin(D) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(CLEAR) {
direction : input;
}
pin(PRESET) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
}
pin(QN) {
direction: output;
function : "IQN";
}
}
}

58
tests/techmap/dfflibmap.ys Normal file
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@ -0,0 +1,58 @@
read_verilog -icells <<EOT
module top(input C, D, S, R, output [9:0] Q);
$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(R), .S(S), .Q(Q[4]));
assign Q[9:5] = ~Q[4:0];
endmodule
EOT
simplemap
design -save orig
#equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -liberty dfflibmap.lib
#equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -prepare -liberty dfflibmap.lib
dfflibmap -prepare -liberty dfflibmap.lib
equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -map-only -liberty dfflibmap.lib
design -load orig
dfflibmap -liberty dfflibmap.lib
clean
select -assert-count 4 t:$_NOT_
select -assert-count 1 t:dffn
select -assert-count 4 t:dffsr
select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i
design -load orig
dfflibmap -prepare -liberty dfflibmap.lib
select -assert-count 9 t:$_NOT_
select -assert-count 1 t:$_DFF_N_
select -assert-count 4 t:$_DFFSR_PPP_
select -assert-none t:$_DFF_N_ t:$_DFFSR_PPP_ t:$_NOT_ %% %n t:* %i
design -load orig
dfflibmap -map-only -liberty dfflibmap.lib
select -assert-count 5 t:$_NOT_
select -assert-count 0 t:dffn
select -assert-count 1 t:dffsr
design -load orig
dfflibmap -prepare -liberty dfflibmap.lib
dfflibmap -map-only -liberty dfflibmap.lib
clean
select -assert-count 4 t:$_NOT_
select -assert-count 1 t:dffn
select -assert-count 4 t:dffsr
select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i