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Removed now obsolete test cases

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Clifford Wolf 2013-11-24 17:30:04 +01:00
parent f71e27dbf1
commit 7eaad2218d
3 changed files with 0 additions and 72 deletions
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2
tests/no-icarus/README
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This directory contains test cases that can't be tested using Icarus Verilog
because they exceed the Verilog subset that is supported by Icarus Verilog.

25
tests/no-icarus/autowire.v
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module test01(a, b, y);
input [3:0] a, b;
output [3:0] y;
assign temp1 = a + b;
assign temp2 = ~temp1;
assign y = temp2;
endmodule
// ------------------------------
module test02(a, b, y);
input [3:0] a, b;
output [3:0] y;
test01 test01_cell(A, B, Y);
assign A = a, B = b, y = Y;
endmodule

45
tests/no-icarus/var_range.v
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module test01(a, b, x, y, z);
input [7:0] a;
input [2:0] b;
output [7:0] x, y;
output z;
assign x = a >> b;
assign y = a[b+7:b];
assign z = a[b];
endmodule
module test02(clk, a, b, x, y, z);
input clk;
input [7:0] a;
input [2:0] b;
output reg [7:0] x, y;
output reg z;
always @(posedge clk) begin
x <= a >> b;
y <= a[b+7:b];
z <= a[b];
end
endmodule
module test03(clk, a, b, x, y);
input clk;
input [2:0] a, b;
output reg [7:0] x;
output reg [9:0] y;
always @(posedge clk)
y[b] <= a;
always @(posedge clk)
y[b+2:b] <= a;
endmodule