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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-06-23 02:30:24 -07:00 • committed by GitHub
commit 7e9e4c7afe
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6 changed files with 83 additions and 7 deletions
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2
frontends/verilog/verilog_lexer.l
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@ -336,7 +336,7 @@ TIME_SCALE_SUFFIX [munpf]?s
}
\" { BEGIN(STRING); }
<STRING>([^\"]|\\.)+ { yymore(); real_location = old_location; }
<STRING>([^\\"]|\\.)+ { yymore(); real_location = old_location; }
<STRING>\" {
BEGIN(0);
char *yystr = strdup(yytext);

7
frontends/verilog/verilog_parser.y
View file

@ -2874,6 +2874,7 @@ behavioral_stmt:
} |
if_attr TOK_IF '(' expr ')' {
AstNode *node = 0;
AstNode *block = new AstNode(AST_BLOCK);
AstNode *context = ast_stack.back();
if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if)) {
AstNode *outer = ast_stack[ast_stack.size() - 2];
@ -2882,8 +2883,10 @@ behavioral_stmt:
// parallel "else if": append condition to outer "if"
node = outer;
log_assert (node->children.size());
ast_stack.pop_back();
delete node->children.back();
node->children.pop_back();
ast_stack.push_back(block);
} else if (outer->get_bool_attribute(ID::full_case))
(*$1)[ID::full_case] = AstNode::mkconst_int(1, false);
}
@ -2894,8 +2897,8 @@ behavioral_stmt:
append_attr(node, $1);
ast_stack.back()->children.push_back(node);
node->children.push_back(node->get_bool_attribute(ID::parallel_case) ? AstNode::mkconst_int(1, false, 1) : expr);
}
AstNode *block = new AstNode(AST_BLOCK);
} else
free_attr($1);
AstNode *cond = new AstNode(AST_COND, node->get_bool_attribute(ID::parallel_case) ? expr : AstNode::mkconst_int(1, false, 1), block);
SET_AST_NODE_LOC(cond, @4, @4);
node->children.push_back(cond);