mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-30 15:00:26 +00:00
Code Activity

Add register file mapping

Browse source
This commit is contained in:
Miodrag Milanovic 2024-05-16 17:15:55 +02:00
parent 11449ec493
commit 7e4aef06e4
3 changed files with 429 additions and 40 deletions
Download patch file Download diff file Expand all files Collapse all files

66
techlibs/nanoxplore/rf_rams_u.txt
View file

@ -1,7 +1,29 @@
ram distributed $__NX_XRFB_64x18_ {
abits 6;
width 18;
cost 10;
# Register-File RAMs for NanoXplore NG-ULTRA
# Dual-port RAMs.
# NX_RFB_U in mode 0 (DPREG)
# NX_RFB_U in mode 2 (NX_XRFB_64x18)
# NX_RFB_U in mode 3 (NX_XRFB_32x36)
ram distributed $__NX_RFB_U_DPREG_ {
option "MODE" 0 {
cost 35;
widthscale 30;
abits 5;
widths 18 global;
}
option "MODE" 2 {
cost 50;
widthscale 30;
abits 6;
widths 18 global;
}
option "MODE" 3 {
cost 50;
widthscale 30;
abits 5;
widths 36 global;
}
init no_undef;
prune_rom;
@ -12,16 +34,36 @@ ram distributed $__NX_XRFB_64x18_ {
}
}
ram distributed $__NX_XRFB_32x36_ {
abits 5;
width 36;
cost 10;
init no_undef;
prune_rom;
# Single-port RAMs.
# NX_RFB_U in mode 1 (SPREG)
ram distributed $__NX_RFB_U_SPREG_ {
cost 30;
widthscale;
abits 5;
width 18;
init no_undef;
prune_rom;
port arsw "RW" {
clock anyedge;
}
}
# Single write dual read RAMs.
# NX_RFB_U in mode 4 (NX_XRFB_2R_1W)
ram distributed $__NX_XRFB_2R_1W_ {
cost 30;
widthscale;
abits 5;
width 18;
init no_undef;
prune_rom;
port sw "W" {
clock anyedge;
}
port ar "R" {
port ar "A" {
}
}
port ar "B" {
}
}