From b72eaf5de5edf8d7a4d9e62b1577d8296f3e93fd Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 9 Jan 2026 18:43:15 +0100
Subject: [PATCH 1/9] add $priority cell

---
 kernel/calc.cc            | 19 +++++++++++++++++++
 kernel/celltypes.h        |  7 ++++++-
 kernel/constids.inc       |  1 +
 kernel/rtlil.cc           | 17 ++++++++++++++++-
 kernel/rtlil.h            |  3 +++
 kernel/satgen.cc          | 33 +++++++++++++++++++++++++++++++++
 passes/tests/test_cell.cc | 16 ++++++++++++++++
 techlibs/common/simlib.v  | 16 ++++++++++++++++
 techlibs/common/techmap.v | 26 ++++++++++++++++++++++++++
 9 files changed, 136 insertions(+), 2 deletions(-)

diff --git a/kernel/calc.cc b/kernel/calc.cc
index 9b0885db9..5ddb230b2 100644
--- a/kernel/calc.cc
+++ b/kernel/calc.cc
@@ -658,6 +658,25 @@ RTLIL::Const RTLIL::const_bmux(const RTLIL::Const &arg1, const RTLIL::Const &arg
 	return t;
 }
 
+RTLIL::Const RTLIL::const_priority(const RTLIL::Const &arg)
+{
+	std::vector<State> t;
+	std::optional<State> first_non_zero = std::nullopt;
+	for (int i = 0; i < GetSize(arg); i++)
+	{
+		RTLIL::State s = arg.at(i);
+		if (first_non_zero && s != State::Sx) {
+			t.push_back(*first_non_zero == State::S1 ? State::S0 : *first_non_zero);
+		} else {
+			t.push_back(s);
+		}
+		if ((!first_non_zero && s != State::S0) || s == State::Sx) {
+			first_non_zero = s;
+		}
+	}
+	return t;
+}
+
 RTLIL::Const RTLIL::const_demux(const RTLIL::Const &arg1, const RTLIL::Const &arg2)
 {
 	int width = GetSize(arg1);
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 34b013dd9..d3aa4399c 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -118,7 +118,7 @@ struct CellTypes
 	void setup_internals_eval()
 	{
 		std::vector<RTLIL::IdString> unary_ops = {
-			ID($not), ID($pos), ID($buf), ID($neg),
+			ID($not), ID($pos), ID($buf), ID($neg), ID($priority),
 			ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
 			ID($logic_not), ID($slice), ID($lut), ID($sop)
 		};
@@ -509,6 +509,11 @@ struct CellTypes
 			return default_ret;
 		}
 
+		if (cell->type == ID($priority))
+		{
+			return const_priority(arg1);
+		}
+
 		bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
 		bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
 		int result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;
diff --git a/kernel/constids.inc b/kernel/constids.inc
index c99aa788d..315944b9d 100644
--- a/kernel/constids.inc
+++ b/kernel/constids.inc
@@ -259,6 +259,7 @@ X($pmux)
 X($pos)
 X($pow)
 X($print)
+X($priority)
 X($recrem)
 X($reduce_and)
 X($reduce_bool)
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 0dbe8bb13..5c0e0cbee 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2646,6 +2646,13 @@ namespace {
 				check_expected();
 				return;
 			}
+			if (cell->type.in(ID($priority))) {
+				param(ID::WIDTH);
+				port(ID::A, param(ID::WIDTH));
+				port(ID::Y, param(ID::WIDTH));
+				check_expected();
+				return;
+			}
 			/*
 			 * Checklist for adding internal cell types
 			 * ========================================
@@ -3961,6 +3968,14 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSp
 	cell->set_src_attribute(src);
 	return cell;
 }
+RTLIL::Cell* RTLIL::Module::addPriority(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, const std::string &src)
+{
+	RTLIL::Cell *cell = addCell(name, ID($priority));
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::Y, sig_y);
+	cell->set_src_attribute(src);
+	return cell;
+}
 
 RTLIL::Cell* RTLIL::Module::addSrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
 		const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
@@ -4503,7 +4518,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 		return;
 	}
 
-	if (type == ID($lut) || type == ID($sop)) {
+	if (type == ID($lut) || type == ID($sop) || type == ID($priority)) {
 		parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
 		return;
 	}
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index e3a5a3bf8..bfd8799d1 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -848,6 +848,7 @@ namespace RTLIL {
 	RTLIL::Const const_pmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);
 	RTLIL::Const const_bmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2);
 	RTLIL::Const const_demux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);
+	RTLIL::Const const_priority    (const RTLIL::Const &arg);
 
 	RTLIL::Const const_bweqx       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);
 	RTLIL::Const const_bwmux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);
@@ -2260,6 +2261,8 @@ public:
 	RTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = "");
 	RTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
 
+	RTLIL::Cell* addPriority (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, const std::string &src = "");
+
 	RTLIL::Cell* addBufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = "");
 	RTLIL::Cell* addNotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = "");
 	RTLIL::Cell* addAndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = "");
diff --git a/kernel/satgen.cc b/kernel/satgen.cc
index f2c1e00c2..2e5b27530 100644
--- a/kernel/satgen.cc
+++ b/kernel/satgen.cc
@@ -430,6 +430,39 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
+	if (cell->type == ID($priority))
+	{
+		std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+		std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
+		std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
+
+		int tmp;
+		if (a.size()) {
+			tmp = a[0];
+			ez->assume(ez->IFF(yy[0], a[0]));
+		}
+		for (size_t i = 1; i < a.size(); i++) {
+			ez->assume(ez->IFF(yy[i], ez->AND(a[i], ez->NOT(tmp))));
+			tmp = ez->OR(tmp, a[i]);
+		}
+		if (model_undef) {
+			std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
+
+			if (a.size()) {
+				tmp = undef_a[0];
+				ez->assume(ez->IFF(undef_y[0], undef_a[0]));
+			}
+			for (size_t i = 1; i < a.size(); i++) {
+				tmp = ez->OR(tmp, undef_a[i]);
+				ez->assume(ez->IFF(undef_y[i], tmp));
+			}
+			undefGating(y, yy, undef_y);
+		}
+
+		return true;
+	}
+
 	if (cell->type.in(ID($pos), ID($buf), ID($neg)))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 4d28e659b..a05d9cb16 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -136,6 +136,21 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		cell->setPort(ID::Y, wire);
 	}
 
+	if (cell_type == ID($priority))
+	{
+		int width = 1 + xorshift32(8 * bloat_factor);
+
+		wire = module->addWire(ID::A);
+		wire->width = width;
+		wire->port_input = true;
+		cell->setPort(ID::A, wire);
+
+		wire = module->addWire(ID::Y);
+		wire->width = width;
+		wire->port_output = true;
+		cell->setPort(ID::Y, wire);
+	}
+
 	if (cell_type == ID($fa))
 	{
 		int width = 1 + xorshift32(8 * bloat_factor);
@@ -1039,6 +1054,7 @@ struct TestCellPass : public Pass {
 		cell_types[ID($mux)] = "*";
 		cell_types[ID($bmux)] = "*";
 		cell_types[ID($demux)] = "*";
+		cell_types[ID($priority)] = "*";
 		// $pmux doesn't work in sat, and is not supported with 'techmap -assert' or
 		// '-simlib'
 		if (nosat && techmap_cmd.compare("aigmap") == 0)
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index e0fb9fbfa..fcdbab555 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -3250,3 +3250,19 @@ parameter WIDTH = 0;
 inout [WIDTH-1:0] Y;
 
 endmodule
+
+// --------------------------------------------------------
+//-
+//-     $priority (A, Y)
+//* group unary
+//-
+//- Priority operator. An output bit is set if the input bit at the same index is set and no lower index input bit is set.
+//-
+module \$priority (A, Y);
+parameter WIDTH = 8;
+input  [WIDTH-1:0] A;
+output [WIDTH-1:0] Y;
+
+assign Y = A & (~A + 1);
+
+endmodule
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index c3364e628..6eb9d01da 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -679,3 +679,29 @@ parameter WIDTH = 0;
 inout [WIDTH-1:0] Y; // This cell is just a maker, so we leave Y undriven
 
 endmodule
+
+(* techmap_celltype = "$priority" *)
+module \$priority (A, Y);
+	parameter WIDTH = 3;
+
+	(* force_downto *)
+	input  [WIDTH-1:0] A;
+	(* force_downto *)
+	output [WIDTH-1:0] Y;
+
+	(* force_downto *)
+	wire [WIDTH-1:0] tmp;
+
+	genvar i;
+	generate
+		if (WIDTH > 0) begin
+			assign tmp[0] = A[0];
+			assign Y[0] = A[0];
+		end
+		for (i = 1; i < WIDTH; i = i + 1) begin
+			assign Y[i] = A[i] & ~tmp[i-1];
+			assign tmp[i] = tmp[i-1] | A[i];
+		end
+	endgenerate
+
+endmodule

From 7f19cf8849075849157e574259393e4be397a273 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 9 Jan 2026 21:02:58 +0100
Subject: [PATCH 2/9] add POLARITY parameter to $priority cell

---
 kernel/calc.cc            |  8 +++++---
 kernel/celltypes.h        |  2 +-
 kernel/constids.inc       |  1 +
 kernel/rtlil.cc           |  1 +
 kernel/rtlil.h            |  2 +-
 kernel/satgen.cc          | 19 ++++++++++++-------
 passes/tests/test_cell.cc |  7 +++++++
 techlibs/common/techmap.v | 16 +++++++++++-----
 8 files changed, 39 insertions(+), 17 deletions(-)

diff --git a/kernel/calc.cc b/kernel/calc.cc
index 5ddb230b2..a1ba5f7c8 100644
--- a/kernel/calc.cc
+++ b/kernel/calc.cc
@@ -658,7 +658,7 @@ RTLIL::Const RTLIL::const_bmux(const RTLIL::Const &arg1, const RTLIL::Const &arg
 	return t;
 }
 
-RTLIL::Const RTLIL::const_priority(const RTLIL::Const &arg)
+RTLIL::Const RTLIL::const_priority(const RTLIL::Const &arg, const RTLIL::Const &polarity)
 {
 	std::vector<State> t;
 	std::optional<State> first_non_zero = std::nullopt;
@@ -666,11 +666,13 @@ RTLIL::Const RTLIL::const_priority(const RTLIL::Const &arg)
 	{
 		RTLIL::State s = arg.at(i);
 		if (first_non_zero && s != State::Sx) {
-			t.push_back(*first_non_zero == State::S1 ? State::S0 : *first_non_zero);
+			auto inactive = polarity[i] == State::S0 ? State::S1 : State::S0;
+			auto val = *first_non_zero == State::Sx ? State::Sx : inactive;
+			t.push_back(val);
 		} else {
 			t.push_back(s);
 		}
-		if ((!first_non_zero && s != State::S0) || s == State::Sx) {
+		if ((!first_non_zero && s == polarity[i]) || s == State::Sx) {
 			first_non_zero = s;
 		}
 	}
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index d3aa4399c..8423deadc 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -511,7 +511,7 @@ struct CellTypes
 
 		if (cell->type == ID($priority))
 		{
-			return const_priority(arg1);
+			return const_priority(arg1, cell->getParam(ID::POLARITY));
 		}
 
 		bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
diff --git a/kernel/constids.inc b/kernel/constids.inc
index 315944b9d..250c8688c 100644
--- a/kernel/constids.inc
+++ b/kernel/constids.inc
@@ -615,6 +615,7 @@ X(PATTERN)
 X(PCIN)
 X(PIPELINE_16x16_MULT_REG1)
 X(PIPELINE_16x16_MULT_REG2)
+X(POLARITY)
 X(PORTID)
 X(PORT_A1_ADDR)
 X(PORT_A1_CLK)
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 5c0e0cbee..65d11cdb2 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2648,6 +2648,7 @@ namespace {
 			}
 			if (cell->type.in(ID($priority))) {
 				param(ID::WIDTH);
+				param(ID::POLARITY);
 				port(ID::A, param(ID::WIDTH));
 				port(ID::Y, param(ID::WIDTH));
 				check_expected();
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index bfd8799d1..747ffa811 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -848,7 +848,7 @@ namespace RTLIL {
 	RTLIL::Const const_pmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);
 	RTLIL::Const const_bmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2);
 	RTLIL::Const const_demux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);
-	RTLIL::Const const_priority    (const RTLIL::Const &arg);
+	RTLIL::Const const_priority    (const RTLIL::Const &arg, const RTLIL::Const &polarity);
 
 	RTLIL::Const const_bweqx       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);
 	RTLIL::Const const_bwmux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);
diff --git a/kernel/satgen.cc b/kernel/satgen.cc
index 2e5b27530..c608a0c19 100644
--- a/kernel/satgen.cc
+++ b/kernel/satgen.cc
@@ -436,26 +436,31 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 		std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
-		int tmp;
+		const Const& polarity = cell->getParam(ID::POLARITY);
+
+		int any_previous_active;
 		if (a.size()) {
-			tmp = a[0];
+			any_previous_active = polarity[0] ? a[0] : ez->NOT(a[0]);
 			ez->assume(ez->IFF(yy[0], a[0]));
 		}
 		for (size_t i = 1; i < a.size(); i++) {
-			ez->assume(ez->IFF(yy[i], ez->AND(a[i], ez->NOT(tmp))));
-			tmp = ez->OR(tmp, a[i]);
+			int inactive_val = !polarity[i] ? ez->CONST_TRUE : ez->CONST_FALSE;
+			int active_val = polarity[i] ? ez->CONST_TRUE : ez->CONST_FALSE;
+			ez->assume(ez->IFF(yy[i], ez->ITE(any_previous_active, inactive_val, a[i])));
+			any_previous_active = ez->OR(any_previous_active, ez->IFF(a[i], active_val));
 		}
 		if (model_undef) {
 			std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
 			std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 
+			int any_previous_undef;
 			if (a.size()) {
-				tmp = undef_a[0];
+				any_previous_undef = undef_a[0];
 				ez->assume(ez->IFF(undef_y[0], undef_a[0]));
 			}
 			for (size_t i = 1; i < a.size(); i++) {
-				tmp = ez->OR(tmp, undef_a[i]);
-				ez->assume(ez->IFF(undef_y[i], tmp));
+				any_previous_undef = ez->OR(any_previous_undef, undef_a[i]);
+				ez->assume(ez->IFF(undef_y[i], any_previous_undef));
 			}
 			undefGating(y, yy, undef_y);
 		}
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index a05d9cb16..b8a4f8d93 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -149,6 +149,13 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 		wire->width = width;
 		wire->port_output = true;
 		cell->setPort(ID::Y, wire);
+
+		RTLIL::SigSpec polarity;
+		for (int i = 0; i < width; i++)
+			polarity.append(xorshift32(2) ? State::S1 : State::S0);
+
+		cell->setParam(ID::POLARITY, polarity.as_const());
+		log("polarity: %s\n", log_signal(polarity));
 	}
 
 	if (cell_type == ID($fa))
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 6eb9d01da..c8f4ec420 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -682,7 +682,8 @@ endmodule
 
 (* techmap_celltype = "$priority" *)
 module \$priority (A, Y);
-	parameter WIDTH = 3;
+	parameter WIDTH = 0;
+	parameter POLARITY = 0;
 
 	(* force_downto *)
 	input  [WIDTH-1:0] A;
@@ -691,16 +692,21 @@ module \$priority (A, Y);
 
 	(* force_downto *)
 	wire [WIDTH-1:0] tmp;
+	(* force_downto *)
+	wire [WIDTH-1:0] A_active;
+	wire [WIDTH-1:0] Y_active;
+	assign A_active = A ^ ~POLARITY;
+	assign Y = Y_active ^ ~POLARITY;
 
 	genvar i;
 	generate
 		if (WIDTH > 0) begin
-			assign tmp[0] = A[0];
-			assign Y[0] = A[0];
+			assign tmp[0] = A_active[0];
+			assign Y_active[0] = A_active[0];
 		end
 		for (i = 1; i < WIDTH; i = i + 1) begin
-			assign Y[i] = A[i] & ~tmp[i-1];
-			assign tmp[i] = tmp[i-1] | A[i];
+			assign Y_active[i] = tmp[i-1] ? 1'b0 : A_active[i];
+			assign tmp[i] = tmp[i-1] | A_active[i];
 		end
 	endgenerate
 

From 0c7afe8e3187b08008242d73100deb61aa2e6447 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 12 Jan 2026 13:21:13 +0100
Subject: [PATCH 3/9] Widen $polarity cell to multiple ports

---
 kernel/calc.cc            | 29 ++++++++++++-----------
 kernel/celltypes.h        |  2 +-
 kernel/constids.inc       |  1 +
 kernel/rtlil.cc           | 10 ++++----
 kernel/rtlil.h            |  2 +-
 kernel/satgen.cc          | 49 +++++++++++++++++++++------------------
 passes/tests/test_cell.cc | 10 +++++---
 techlibs/common/techmap.v | 29 ++++++++++++-----------
 8 files changed, 74 insertions(+), 58 deletions(-)

diff --git a/kernel/calc.cc b/kernel/calc.cc
index a1ba5f7c8..589fd4aa7 100644
--- a/kernel/calc.cc
+++ b/kernel/calc.cc
@@ -658,22 +658,25 @@ RTLIL::Const RTLIL::const_bmux(const RTLIL::Const &arg1, const RTLIL::Const &arg
 	return t;
 }
 
-RTLIL::Const RTLIL::const_priority(const RTLIL::Const &arg, const RTLIL::Const &polarity)
+RTLIL::Const RTLIL::const_priority(const RTLIL::Const &arg, int p_width, const RTLIL::Const &polarity)
 {
 	std::vector<State> t;
-	std::optional<State> first_non_zero = std::nullopt;
-	for (int i = 0; i < GetSize(arg); i++)
+	for (int offset = 0; offset < GetSize(arg); offset += p_width)
 	{
-		RTLIL::State s = arg.at(i);
-		if (first_non_zero && s != State::Sx) {
-			auto inactive = polarity[i] == State::S0 ? State::S1 : State::S0;
-			auto val = *first_non_zero == State::Sx ? State::Sx : inactive;
-			t.push_back(val);
-		} else {
-			t.push_back(s);
-		}
-		if ((!first_non_zero && s == polarity[i]) || s == State::Sx) {
-			first_non_zero = s;
+		std::optional<State> first_non_zero = std::nullopt;
+		for (int i = offset; i < offset + p_width; i++)
+		{
+			RTLIL::State s = arg.at(i);
+			if (first_non_zero && s != State::Sx) {
+				auto inactive = polarity[i] == State::S0 ? State::S1 : State::S0;
+				auto val = *first_non_zero == State::Sx ? State::Sx : inactive;
+				t.push_back(val);
+			} else {
+				t.push_back(s);
+			}
+			if ((!first_non_zero && s == polarity[i]) || s == State::Sx) {
+				first_non_zero = s;
+			}
 		}
 	}
 	return t;
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 8423deadc..0f15ca61d 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -511,7 +511,7 @@ struct CellTypes
 
 		if (cell->type == ID($priority))
 		{
-			return const_priority(arg1, cell->getParam(ID::POLARITY));
+			return const_priority(arg1, cell->getParam(ID::P_WIDTH).as_int(), cell->getParam(ID::POLARITY));
 		}
 
 		bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
diff --git a/kernel/constids.inc b/kernel/constids.inc
index 250c8688c..e189d804d 100644
--- a/kernel/constids.inc
+++ b/kernel/constids.inc
@@ -680,6 +680,7 @@ X(PRODUCT_NEGATED)
 X(P_BYPASS)
 X(P_EN)
 X(P_SRST_N)
+X(P_WIDTH)
 X(Q)
 X(QL_DSP2)
 X(R)
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 65d11cdb2..4eef695a3 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2648,9 +2648,10 @@ namespace {
 			}
 			if (cell->type.in(ID($priority))) {
 				param(ID::WIDTH);
+				param(ID::P_WIDTH);
 				param(ID::POLARITY);
-				port(ID::A, param(ID::WIDTH));
-				port(ID::Y, param(ID::WIDTH));
+				port(ID::A, param(ID::P_WIDTH)*param(ID::WIDTH));
+				port(ID::Y, param(ID::P_WIDTH)*param(ID::WIDTH));
 				check_expected();
 				return;
 			}
@@ -4501,7 +4502,8 @@ void RTLIL::Cell::check()
 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 {
 	if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
-			type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
+			type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:")||
+			type.begins_with("$priority"))
 		return;
 
 	if (type == ID($buf) || type == ID($mux) || type == ID($pmux) || type == ID($bmux) || type == ID($bwmux) || type == ID($bweqx)) {
@@ -4519,7 +4521,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 		return;
 	}
 
-	if (type == ID($lut) || type == ID($sop) || type == ID($priority)) {
+	if (type == ID($lut) || type == ID($sop)) {
 		parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
 		return;
 	}
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 747ffa811..f65229ee0 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -848,7 +848,7 @@ namespace RTLIL {
 	RTLIL::Const const_pmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);
 	RTLIL::Const const_bmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2);
 	RTLIL::Const const_demux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);
-	RTLIL::Const const_priority    (const RTLIL::Const &arg, const RTLIL::Const &polarity);
+	RTLIL::Const const_priority    (const RTLIL::Const &arg, int p_width, const RTLIL::Const &polarity);
 
 	RTLIL::Const const_bweqx       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);
 	RTLIL::Const const_bwmux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);
diff --git a/kernel/satgen.cc b/kernel/satgen.cc
index c608a0c19..c9c0fed4f 100644
--- a/kernel/satgen.cc
+++ b/kernel/satgen.cc
@@ -437,32 +437,35 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
 		const Const& polarity = cell->getParam(ID::POLARITY);
+		int p_width = cell->getParam(ID::P_WIDTH).as_int();
 
-		int any_previous_active;
-		if (a.size()) {
-			any_previous_active = polarity[0] ? a[0] : ez->NOT(a[0]);
-			ez->assume(ez->IFF(yy[0], a[0]));
-		}
-		for (size_t i = 1; i < a.size(); i++) {
-			int inactive_val = !polarity[i] ? ez->CONST_TRUE : ez->CONST_FALSE;
-			int active_val = polarity[i] ? ez->CONST_TRUE : ez->CONST_FALSE;
-			ez->assume(ez->IFF(yy[i], ez->ITE(any_previous_active, inactive_val, a[i])));
-			any_previous_active = ez->OR(any_previous_active, ez->IFF(a[i], active_val));
-		}
-		if (model_undef) {
-			std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
-			std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
+		for (size_t offset = 0; offset < a.size(); offset += p_width) {
+			int any_previous_active;
+			if (p_width) {
+				any_previous_active = polarity[offset] ? a[offset] : ez->NOT(a[offset]);
+				ez->assume(ez->IFF(yy[offset], a[offset]));
+			}
+			for (size_t i = offset + 1; i < offset + p_width; i++) {
+				int inactive_val = !polarity[i] ? ez->CONST_TRUE : ez->CONST_FALSE;
+				int active_val = polarity[i] ? ez->CONST_TRUE : ez->CONST_FALSE;
+				ez->assume(ez->IFF(yy[i], ez->ITE(any_previous_active, inactive_val, a[i])));
+				any_previous_active = ez->OR(any_previous_active, ez->IFF(a[i], active_val));
+			}
+			if (model_undef) {
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 
-			int any_previous_undef;
-			if (a.size()) {
-				any_previous_undef = undef_a[0];
-				ez->assume(ez->IFF(undef_y[0], undef_a[0]));
+				int any_previous_undef;
+				if (p_width) {
+					any_previous_undef = undef_a[offset];
+					ez->assume(ez->IFF(undef_y[offset], undef_a[offset]));
+				}
+				for (size_t i = offset + 1; i < offset + p_width; i++) {
+					any_previous_undef = ez->OR(any_previous_undef, undef_a[i]);
+					ez->assume(ez->IFF(undef_y[i], any_previous_undef));
+				}
+				undefGating(y, yy, undef_y);
 			}
-			for (size_t i = 1; i < a.size(); i++) {
-				any_previous_undef = ez->OR(any_previous_undef, undef_a[i]);
-				ez->assume(ez->IFF(undef_y[i], any_previous_undef));
-			}
-			undefGating(y, yy, undef_y);
 		}
 
 		return true;
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index b8a4f8d93..a3faf3945 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -138,24 +138,28 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 
 	if (cell_type == ID($priority))
 	{
+		int priority_width = 1 + xorshift32(8 * bloat_factor);
 		int width = 1 + xorshift32(8 * bloat_factor);
+		int port_width = width * priority_width;
 
 		wire = module->addWire(ID::A);
-		wire->width = width;
+		wire->width = port_width;
 		wire->port_input = true;
 		cell->setPort(ID::A, wire);
 
 		wire = module->addWire(ID::Y);
-		wire->width = width;
+		wire->width = port_width;
 		wire->port_output = true;
 		cell->setPort(ID::Y, wire);
 
 		RTLIL::SigSpec polarity;
-		for (int i = 0; i < width; i++)
+		for (int i = 0; i < port_width; i++)
 			polarity.append(xorshift32(2) ? State::S1 : State::S0);
 
 		cell->setParam(ID::POLARITY, polarity.as_const());
 		log("polarity: %s\n", log_signal(polarity));
+		cell->setParam(ID::P_WIDTH, priority_width);
+		cell->setParam(ID::WIDTH, width);
 	}
 
 	if (cell_type == ID($fa))
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index c8f4ec420..5b6665c92 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -683,30 +683,33 @@ endmodule
 (* techmap_celltype = "$priority" *)
 module \$priority (A, Y);
 	parameter WIDTH = 0;
+	parameter P_WIDTH = 0;
 	parameter POLARITY = 0;
 
 	(* force_downto *)
-	input  [WIDTH-1:0] A;
+	input  [P_WIDTH*WIDTH-1:0] A;
 	(* force_downto *)
-	output [WIDTH-1:0] Y;
+	output [P_WIDTH*WIDTH-1:0] Y;
 
 	(* force_downto *)
-	wire [WIDTH-1:0] tmp;
+	wire [P_WIDTH*WIDTH-1:0] tmp;
 	(* force_downto *)
-	wire [WIDTH-1:0] A_active;
-	wire [WIDTH-1:0] Y_active;
+	wire [P_WIDTH*WIDTH-1:0] A_active;
+	wire [P_WIDTH*WIDTH-1:0] Y_active;
 	assign A_active = A ^ ~POLARITY;
 	assign Y = Y_active ^ ~POLARITY;
 
-	genvar i;
+	genvar i, offset;
 	generate
-		if (WIDTH > 0) begin
-			assign tmp[0] = A_active[0];
-			assign Y_active[0] = A_active[0];
-		end
-		for (i = 1; i < WIDTH; i = i + 1) begin
-			assign Y_active[i] = tmp[i-1] ? 1'b0 : A_active[i];
-			assign tmp[i] = tmp[i-1] | A_active[i];
+		for (offset = 0; offset < P_WIDTH*WIDTH; offset = offset + P_WIDTH) begin
+			if (P_WIDTH > 0) begin
+				assign tmp[offset] = A_active[offset];
+				assign Y_active[offset] = A_active[offset];
+			end
+			for (i = offset + 1; i < offset + P_WIDTH; i = i + 1) begin
+				assign Y_active[i] = tmp[i - 1] ? 1'b0 : A_active[i];
+				assign tmp[i] = tmp[i - 1] | A_active[i];
+			end
 		end
 	endgenerate
 

From c7ea80661daaa981421c5bb447d05eb6fb78bdde Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 12 Jan 2026 22:24:24 +0100
Subject: [PATCH 4/9] wip simlib

---
 techlibs/common/simlib.v | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index fcdbab555..1c0e16735 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -3259,10 +3259,16 @@ endmodule
 //- Priority operator. An output bit is set if the input bit at the same index is set and no lower index input bit is set.
 //-
 module \$priority (A, Y);
-parameter WIDTH = 8;
-input  [WIDTH-1:0] A;
-output [WIDTH-1:0] Y;
-
-assign Y = A & (~A + 1);
+	parameter WIDTH = 0;
+	parameter P_WIDTH = 0;
+	parameter POLARITY = 0;
+	input  [P_WIDTH*WIDTH-1:0] A;
+	output [P_WIDTH*WIDTH-1:0] Y;
 
+	genvar offset;
+	generate
+		for (offset = 0; offset < P_WIDTH*WIDTH; offset = offset + P_WIDTH) begin
+			assign Y[offset : offset+P_WIDTH-1] = POLARITY[offset : offset+P_WIDTH-1] ^ ((A[offset : offset+P_WIDTH-1] ^ POLARITY[offset : offset+P_WIDTH-1]) & (~(A[offset : offset+P_WIDTH-1] ^ POLARITY[offset : offset+P_WIDTH-1]) + 1));
+		end
+	endgenerate
 endmodule

From 49b35aa1b5706040300dccac4eaf34de39b75ce1 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 16 Jan 2026 12:15:51 +0100
Subject: [PATCH 5/9] proc_dff: refactor

---
 passes/proc/proc_dff.cc | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index 06c740a88..3ac9c9825 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -53,13 +53,19 @@ RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
 	return lvalue;
 }
 
-void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity,
-		std::vector<std::pair<RTLIL::SigSpec, RTLIL::SyncRule*>> &async_rules, RTLIL::Process *proc)
+struct DSigs {
+	RTLIL::SigSpec d;
+	RTLIL::SigSpec q;
+	RTLIL::SigSpec clk;
+};
+using Rules = std::vector<std::pair<RTLIL::SigSpec, RTLIL::SyncRule*>>;
+void gen_dffsr_complex(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
+		Rules &async_rules, RTLIL::Process *proc)
 {
 	// A signal should be set/cleared if there is a load trigger that is enabled
 	// such that the load value is 1/0 and it is the highest priority trigger
-	RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size());
-	RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size());
+	RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sigs.d.size());
+	RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sigs.d.size());
 
 	// Reverse iterate through the rules as the first ones are the highest priority
 	// so need to be at the top of the mux trees
@@ -81,7 +87,7 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec
 	std::stringstream sstr;
 	sstr << "$procdff$" << (autoidx++);
 
-	RTLIL::Cell *cell = mod->addDffsr(sstr.str(), clk, sig_sr_set, sig_sr_clr, sig_d, sig_q, clk_polarity);
+	RTLIL::Cell *cell = mod->addDffsr(sstr.str(), sigs.clk, sig_sr_set, sig_sr_clr, sigs.d, sigs.q, clk_polarity);
 	cell->attributes = proc->attributes;
 
 	log("  created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
@@ -261,7 +267,9 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 		if (async_rules.size() > 1)
 		{
 			log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
-			gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, async_rules, proc);
+			DSigs sigs {insig, sig, sync_edge->signal};
+			bool clk_pol = sync_edge->type == RTLIL::SyncType::STp;
+			gen_dffsr_complex(mod, sigs, clk_pol, async_rules, proc);
 			continue;
 		}
 

From 6f7aa96080d69c0b1646399e4c5bd1f20c475ddc Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 16 Jan 2026 16:14:31 +0100
Subject: [PATCH 6/9] proc_dff: emit $dffsr with $priority instead of mux tree

---
 passes/proc/proc_dff.cc | 124 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 123 insertions(+), 1 deletion(-)

diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index 3ac9c9825..72f2dbf75 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -17,7 +17,9 @@
  *
  */
 
+#include "backends/rtlil/rtlil_backend.h"
 #include "kernel/register.h"
+#include "kernel/rtlil.h"
 #include "kernel/sigtools.h"
 #include "kernel/consteval.h"
 #include "kernel/log.h"
@@ -59,6 +61,7 @@ struct DSigs {
 	RTLIL::SigSpec clk;
 };
 using Rules = std::vector<std::pair<RTLIL::SigSpec, RTLIL::SyncRule*>>;
+
 void gen_dffsr_complex(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 		Rules &async_rules, RTLIL::Process *proc)
 {
@@ -94,6 +97,124 @@ void gen_dffsr_complex(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 			cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
 }
 
+void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
+		Rules &async_rules, ConstEval& ce, RTLIL::Process *proc)
+{
+	RTLIL::SigSpec sig_sr_set;
+	RTLIL::SigSpec sig_sr_clr;
+
+	struct BitRule {
+		SigBit trig;
+		bool trig_polarity; // true = active high, false = active low
+		bool effect; // true = set, false = reset
+	};
+	std::vector<std::vector<BitRule>> bit_rules(sigs.d.size());
+	// For checking consistent per-bit set/reset edges and bailing out on inconsistent
+	std::optional<bool> bit_set_pol;
+	std::optional<bool> bit_reset_pol;
+
+	for (auto it = async_rules.cbegin(); it != async_rules.cend(); it++)
+	{
+		const auto& [sync_value, rule] = *it;
+		log_debug("sync_value %s, rule:\n", log_signal(sync_value));
+
+		for (int i = 0; i < sigs.d.size(); i++) {
+			log_debug("rule->signal %s\n", log_signal(rule->signal));
+			log_debug(rule->signal.size() == 1);
+			SigSpec value_bit = sync_value[i];
+			if (sync_value[i] == sigs.q[i]) {
+				log_debug("%s is %s\n", log_signal(sync_value[i]), log_signal(sigs.q[i]));
+				continue;
+			}
+			if (!ce.eval(value_bit)) {
+				log_debug("non-const %s\n", log_signal(sync_value[i]));
+				gen_dffsr_complex(mod, sigs, clk_polarity, async_rules, proc);
+				return;
+			}
+			bool effect = ce.values_map(value_bit).as_const().as_bool();
+			bool trig_pol = rule->type == RTLIL::SyncType::ST1;
+			while (bit_rules.size() <= (size_t) i)
+				bit_rules.push_back({});
+			bit_rules[i].push_back({rule->signal[0], trig_pol, effect});
+
+			bool set_inconsistent = effect && bit_set_pol && (*bit_set_pol != trig_pol);
+			bool reset_inconsistent = !effect && bit_reset_pol && (*bit_reset_pol != trig_pol);
+			if (set_inconsistent || reset_inconsistent) {
+				gen_dffsr_complex(mod, sigs, clk_polarity, async_rules, proc);
+				return;
+			}
+			if (effect) {
+				bit_set_pol = trig_pol;
+			} else {
+				bit_reset_pol = trig_pol;
+			}
+		}
+	}
+
+	log_assert(bit_set_pol != std::nullopt);
+	log_assert(bit_reset_pol != std::nullopt);
+
+	RTLIL::Wire* prioritized = mod->addWire(NEW_ID, sigs.d.size() * async_rules.size());
+	RTLIL::Cell* priority = mod->addPriority(NEW_ID, SigSpec(), prioritized);
+	priority->setParam(ID::WIDTH, sigs.d.size());
+	priority->setParam(ID::P_WIDTH, async_rules.size());
+	SigSpec priority_in;
+	std::vector<RTLIL::State> priority_pol;
+	for (int i = 0; i < sigs.d.size(); i++) {
+		log_debug("bit %d:\n", i);
+		SigSpec bit_sets;
+		SigSpec bit_resets;
+		for (auto rule : bit_rules[i]) {
+			log_debug("if %s == %d then set %d\n", log_signal(rule.trig), rule.trig_polarity, rule.effect);
+			priority_in.append(rule.trig);
+			priority_pol.push_back(RTLIL::State(rule.trig_polarity));
+			if (rule.effect)
+				bit_sets.append(SigBit(prioritized, priority_in.size() - 1));
+			else
+				bit_resets.append(SigBit(prioritized, priority_in.size() - 1));
+		}
+		std::optional<SigBit> set;
+		if (bit_sets.size()) {
+			if (bit_sets.size() == 1) {
+				set = bit_sets[0];
+			} else {
+				set = mod->addWire(NEW_ID);
+				// Polarities are consistent, as guaranteed by check prior
+				(bit_rules[i][0].trig_polarity ? mod->addReduceOr(NEW_ID, bit_sets, *set) : mod->addReduceAnd(NEW_ID, bit_sets, *set))->attributes = proc->attributes;
+			}
+		}
+		std::optional<SigBit> reset;
+		if (bit_resets.size()) {
+			if (bit_resets.size() == 1) {
+				reset = bit_resets[0];
+			} else {
+				reset = mod->addWire(NEW_ID);
+				(bit_rules[i][0].trig_polarity ? mod->addReduceOr(NEW_ID, bit_resets, *reset) : mod->addReduceAnd(NEW_ID, bit_resets, *reset))->attributes = proc->attributes;
+			}
+		}
+		if (set)
+			sig_sr_set.append(*set);
+		else
+			sig_sr_set.append(*bit_set_pol ? Const(0, 1) : Const(1, 1));
+		if (reset)
+			sig_sr_clr.append(*reset);
+		else
+			sig_sr_clr.append(*bit_reset_pol ? Const(0, 1) : Const(1, 1));
+	}
+	priority->setPort(ID::A, priority_in);
+	priority->setParam(ID::POLARITY, priority_pol);
+
+	std::stringstream sstr;
+	sstr << "$procdff$" << (autoidx++);
+
+	RTLIL::Cell *cell = mod->addDffsr(sstr.str(), sigs.clk, sig_sr_set, sig_sr_clr, sigs.d, sigs.q, clk_polarity);
+	cell->attributes = proc->attributes;
+	priority->attributes = proc->attributes;
+
+	log("  created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
+			cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
+}
+
 void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_out,
 		bool clk_polarity, bool set_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec set, RTLIL::Process *proc)
 {
@@ -269,7 +390,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 			log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
 			DSigs sigs {insig, sig, sync_edge->signal};
 			bool clk_pol = sync_edge->type == RTLIL::SyncType::STp;
-			gen_dffsr_complex(mod, sigs, clk_pol, async_rules, proc);
+			gen_dffsr(mod, sigs, clk_pol, async_rules, ce, proc);
 			continue;
 		}
 
@@ -313,6 +434,7 @@ struct ProcDffPass : public Pass {
 		log_header(design, "Executing PROC_DFF pass (convert process syncs to FFs).\n");
 
 		extra_args(args, 1, design);
+		Pass::call(design, "dump");
 
 		for (auto mod : design->all_selected_modules()) {
 			ConstEval ce(mod);

From 6c2d3642b411e190c1cff39f91e0badf02134c1c Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 16 Jan 2026 16:42:42 +0100
Subject: [PATCH 7/9] proc_dff: fix enables for $dffsr

---
 passes/proc/proc_dff.cc | 33 +++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 12 deletions(-)

diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index 72f2dbf75..d07976a18 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -108,7 +108,8 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 		bool trig_polarity; // true = active high, false = active low
 		bool effect; // true = set, false = reset
 	};
-	std::vector<std::vector<BitRule>> bit_rules(sigs.d.size());
+	// nullopt rule = "this bit is not assigned to in this rule"
+	std::vector<std::vector<std::optional<BitRule>>> bit_rules(sigs.d.size());
 	// For checking consistent per-bit set/reset edges and bailing out on inconsistent
 	std::optional<bool> bit_set_pol;
 	std::optional<bool> bit_reset_pol;
@@ -116,14 +117,14 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 	for (auto it = async_rules.cbegin(); it != async_rules.cend(); it++)
 	{
 		const auto& [sync_value, rule] = *it;
-		log_debug("sync_value %s, rule:\n", log_signal(sync_value));
-
 		for (int i = 0; i < sigs.d.size(); i++) {
-			log_debug("rule->signal %s\n", log_signal(rule->signal));
-			log_debug(rule->signal.size() == 1);
+			log_assert(rule->signal.size() == 1);
 			SigSpec value_bit = sync_value[i];
 			if (sync_value[i] == sigs.q[i]) {
 				log_debug("%s is %s\n", log_signal(sync_value[i]), log_signal(sigs.q[i]));
+				while (bit_rules.size() <= (size_t) i)
+					bit_rules.push_back({});
+				bit_rules[i].push_back(std::nullopt);
 				continue;
 			}
 			if (!ce.eval(value_bit)) {
@@ -135,7 +136,8 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 			bool trig_pol = rule->type == RTLIL::SyncType::ST1;
 			while (bit_rules.size() <= (size_t) i)
 				bit_rules.push_back({});
-			bit_rules[i].push_back({rule->signal[0], trig_pol, effect});
+			BitRule bit_rule {rule->signal[0], trig_pol, effect};
+			bit_rules[i].push_back(bit_rule);
 
 			bool set_inconsistent = effect && bit_set_pol && (*bit_set_pol != trig_pol);
 			bool reset_inconsistent = !effect && bit_reset_pol && (*bit_reset_pol != trig_pol);
@@ -165,10 +167,17 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 		SigSpec bit_sets;
 		SigSpec bit_resets;
 		for (auto rule : bit_rules[i]) {
-			log_debug("if %s == %d then set %d\n", log_signal(rule.trig), rule.trig_polarity, rule.effect);
-			priority_in.append(rule.trig);
-			priority_pol.push_back(RTLIL::State(rule.trig_polarity));
-			if (rule.effect)
+			if (!rule) {
+				// Unused bit due to no assignment to this bit from this rule
+				log_debug("Unused bit due to no assignment to this bit from this rule\n");
+				priority_in.append(Const(0, 1));
+				priority_pol.push_back(RTLIL::State::S0);
+				continue;
+			}
+			log_debug("if %s == %d then set %d\n", log_signal(rule->trig), rule->trig_polarity, rule->effect);
+			priority_in.append(rule->trig);
+			priority_pol.push_back(RTLIL::State(rule->trig_polarity));
+			if (rule->effect)
 				bit_sets.append(SigBit(prioritized, priority_in.size() - 1));
 			else
 				bit_resets.append(SigBit(prioritized, priority_in.size() - 1));
@@ -180,7 +189,7 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 			} else {
 				set = mod->addWire(NEW_ID);
 				// Polarities are consistent, as guaranteed by check prior
-				(bit_rules[i][0].trig_polarity ? mod->addReduceOr(NEW_ID, bit_sets, *set) : mod->addReduceAnd(NEW_ID, bit_sets, *set))->attributes = proc->attributes;
+				(*bit_set_pol ? mod->addReduceOr(NEW_ID, bit_sets, *set) : mod->addReduceAnd(NEW_ID, bit_sets, *set))->attributes = proc->attributes;
 			}
 		}
 		std::optional<SigBit> reset;
@@ -189,7 +198,7 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 				reset = bit_resets[0];
 			} else {
 				reset = mod->addWire(NEW_ID);
-				(bit_rules[i][0].trig_polarity ? mod->addReduceOr(NEW_ID, bit_resets, *reset) : mod->addReduceAnd(NEW_ID, bit_resets, *reset))->attributes = proc->attributes;
+				(*bit_reset_pol ? mod->addReduceOr(NEW_ID, bit_resets, *reset) : mod->addReduceAnd(NEW_ID, bit_resets, *reset))->attributes = proc->attributes;
 			}
 		}
 		if (set)

From 0d85044f6aa13f97922875ecb23d57610873dc59 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 16 Jan 2026 23:30:41 +0100
Subject: [PATCH 8/9] proc_dff: uniquing $priority

---
 passes/proc/proc_dff.cc | 197 ++++++++++++++++++++++++++--------------
 1 file changed, 129 insertions(+), 68 deletions(-)

diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index d07976a18..998d18bca 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -23,11 +23,25 @@
 #include "kernel/sigtools.h"
 #include "kernel/consteval.h"
 #include "kernel/log.h"
+#include "kernel/yosys_common.h"
+#include <optional>
 #include <sstream>
 #include <stdlib.h>
 #include <stdio.h>
 
 USING_YOSYS_NAMESPACE
+
+struct BitRule {
+	SigBit trig;
+	bool trig_polarity; // true = active high, false = active low
+	bool effect; // true = set, false = reset
+
+	bool operator==(const BitRule& other) const { return trig == other.trig && trig_polarity == other.trig_polarity && effect == other.effect; }
+	[[nodiscard]] Hasher hash_into(Hasher h) const { // No, this fluff doesn't deserve more lines. It's not meant to be read.
+		h.eat(trig); h.eat(trig_polarity); h.eat(effect); return h; }
+};
+template<> struct std::hash<std::vector<BitRule>> {std::size_t operator()(const std::vector<BitRule>& r) const noexcept { Hasher h; for (auto& rr : r) h.eat(rr); return (size_t)h.yield(); } };
+
 PRIVATE_NAMESPACE_BEGIN
 
 RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
@@ -62,6 +76,9 @@ struct DSigs {
 };
 using Rules = std::vector<std::pair<RTLIL::SigSpec, RTLIL::SyncRule*>>;
 
+/**
+ * Generates odd $dffsr wirh priority and ALOAD implemented with muxes
+ */
 void gen_dffsr_complex(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 		Rules &async_rules, RTLIL::Process *proc)
 {
@@ -97,22 +114,19 @@ void gen_dffsr_complex(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 			cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
 }
 
+/**
+ * Generates $dffsr wirh $priority cells
+ */
 void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 		Rules &async_rules, ConstEval& ce, RTLIL::Process *proc)
 {
 	RTLIL::SigSpec sig_sr_set;
 	RTLIL::SigSpec sig_sr_clr;
-
-	struct BitRule {
-		SigBit trig;
-		bool trig_polarity; // true = active high, false = active low
-		bool effect; // true = set, false = reset
-	};
 	// nullopt rule = "this bit is not assigned to in this rule"
 	std::vector<std::vector<std::optional<BitRule>>> bit_rules(sigs.d.size());
 	// For checking consistent per-bit set/reset edges and bailing out on inconsistent
-	std::optional<bool> bit_set_pol;
-	std::optional<bool> bit_reset_pol;
+	std::optional<bool> set_pol;
+	std::optional<bool> reset_pol;
 
 	for (auto it = async_rules.cbegin(); it != async_rules.cend(); it++)
 	{
@@ -128,6 +142,7 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 				continue;
 			}
 			if (!ce.eval(value_bit)) {
+				// ALOAD, mux tree time
 				log_debug("non-const %s\n", log_signal(sync_value[i]));
 				gen_dffsr_complex(mod, sigs, clk_polarity, async_rules, proc);
 				return;
@@ -139,86 +154,132 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 			BitRule bit_rule {rule->signal[0], trig_pol, effect};
 			bit_rules[i].push_back(bit_rule);
 
-			bool set_inconsistent = effect && bit_set_pol && (*bit_set_pol != trig_pol);
-			bool reset_inconsistent = !effect && bit_reset_pol && (*bit_reset_pol != trig_pol);
+			bool set_inconsistent = effect && set_pol && (*set_pol != trig_pol);
+			bool reset_inconsistent = !effect && reset_pol && (*reset_pol != trig_pol);
 			if (set_inconsistent || reset_inconsistent) {
+				// Mixed polarities, mux tree time
 				gen_dffsr_complex(mod, sigs, clk_polarity, async_rules, proc);
 				return;
 			}
 			if (effect) {
-				bit_set_pol = trig_pol;
+				set_pol = trig_pol;
 			} else {
-				bit_reset_pol = trig_pol;
+				reset_pol = trig_pol;
 			}
 		}
 	}
 
-	log_assert(bit_set_pol != std::nullopt);
-	log_assert(bit_reset_pol != std::nullopt);
+	log_assert(set_pol != std::nullopt);
+	log_assert(reset_pol != std::nullopt);
 
-	RTLIL::Wire* prioritized = mod->addWire(NEW_ID, sigs.d.size() * async_rules.size());
-	RTLIL::Cell* priority = mod->addPriority(NEW_ID, SigSpec(), prioritized);
-	priority->setParam(ID::WIDTH, sigs.d.size());
-	priority->setParam(ID::P_WIDTH, async_rules.size());
-	SigSpec priority_in;
-	std::vector<RTLIL::State> priority_pol;
+	struct Builder {
+		using BitControl = std::pair<std::optional<SigBit>, std::optional<SigBit>>;
+		std::vector<RTLIL::Cell*> cells {};
+		std::unordered_map<std::vector<BitRule>, BitControl> map = {};
+		RTLIL::Module* mod;
+		RTLIL::Wire* prioritized;
+		RTLIL::SigSpec priority_in;
+		std::vector<RTLIL::State> priority_pol;
+		bool set_pol, reset_pol;
+		Builder(RTLIL::Module* mod, size_t rule_count, bool s, bool r) : mod(mod), set_pol(s), reset_pol(r) {
+			prioritized = mod->addWire(NEW_ID, 0);
+			RTLIL::Cell* priority = mod->addPriority(NEW_ID, SigSpec(), prioritized);
+			priority->setParam(ID::P_WIDTH, rule_count);
+			cells.push_back(priority);
+		}
+		BitControl build(std::vector<std::optional<BitRule>>& rules) {
+			std::vector<BitRule> applicable;
+			int skips = 0;
+			for (auto rule : rules) {
+				if (rule) {
+					applicable.push_back(*rule);
+				} else {
+					skips += 1;
+					log_debug("Unused bit due to no assignment to this bit from this rule\n");
+				}
+			}
+			log_debug("count?\n");
+			if (map.count(applicable)) {
+				log_debug("hit!\n");
+				return map[applicable];
+			}
+
+			SigSpec bit_sets;
+			SigSpec bit_resets;
+
+			// Construct applicable rules
+			for (auto rule : applicable) {
+				log_debug("if %s == %d then set %d\n", log_signal(rule.trig), rule.trig_polarity, rule.effect);
+				prioritized->width++;
+				priority_in.append(rule.trig);
+				priority_pol.push_back(RTLIL::State(rule.trig_polarity));
+				if (rule.effect)
+					bit_sets.append(SigBit(prioritized, priority_in.size() - 1));
+				else
+					bit_resets.append(SigBit(prioritized, priority_in.size() - 1));
+			}
+
+			// Stuff $priority with unused bits
+			priority_in.append(Const(0, skips));
+			for (int i = 0; i < skips; i++) {
+				prioritized->width++;
+				priority_pol.push_back(RTLIL::State::S0);
+			}
+
+			std::optional<SigBit> set;
+			if (bit_sets.size()) {
+				if (bit_sets.size() == 1) {
+					set = bit_sets[0];
+				} else {
+					set = mod->addWire(NEW_ID);
+					// Polarities are consistent, as guaranteed by check prior
+					cells.push_back(set_pol ? mod->addReduceOr(NEW_ID, bit_sets, *set) : mod->addReduceAnd(NEW_ID, bit_sets, *set));
+				}
+			}
+			std::optional<SigBit> reset;
+			if (bit_resets.size()) {
+				if (bit_resets.size() == 1) {
+					reset = bit_resets[0];
+				} else {
+					reset = mod->addWire(NEW_ID);
+					cells.push_back(reset_pol ? mod->addReduceOr(NEW_ID, bit_resets, *reset) : mod->addReduceAnd(NEW_ID, bit_resets, *reset));
+				}
+			}
+			if (!set)
+				set = set_pol ? RTLIL::State::S0 : RTLIL::State::S1;
+			if (!reset)
+				reset = reset_pol ? RTLIL::State::S0 : RTLIL::State::S1;
+
+			auto ret = std::make_pair(set, reset);
+			map[applicable] = ret;
+			return ret;
+
+		}
+		void finish(RTLIL::Process* proc) {
+			prioritized->attributes = proc->attributes;
+			for (auto* cell : cells)
+				cell->attributes = proc->attributes;
+
+			cells[0]->setPort(ID::A, priority_in);
+			cells[0]->setPort(ID::Y, prioritized); // fixup (previously zero-width)
+			cells[0]->setParam(ID::POLARITY, priority_pol);
+			cells[0]->setParam(ID::WIDTH, cells[0]->getPort(ID::A).size() / cells[0]->getParam(ID::P_WIDTH).as_int());
+		}
+	};
+	Builder builder(mod, async_rules.size(), *set_pol, *reset_pol);
 	for (int i = 0; i < sigs.d.size(); i++) {
 		log_debug("bit %d:\n", i);
-		SigSpec bit_sets;
-		SigSpec bit_resets;
-		for (auto rule : bit_rules[i]) {
-			if (!rule) {
-				// Unused bit due to no assignment to this bit from this rule
-				log_debug("Unused bit due to no assignment to this bit from this rule\n");
-				priority_in.append(Const(0, 1));
-				priority_pol.push_back(RTLIL::State::S0);
-				continue;
-			}
-			log_debug("if %s == %d then set %d\n", log_signal(rule->trig), rule->trig_polarity, rule->effect);
-			priority_in.append(rule->trig);
-			priority_pol.push_back(RTLIL::State(rule->trig_polarity));
-			if (rule->effect)
-				bit_sets.append(SigBit(prioritized, priority_in.size() - 1));
-			else
-				bit_resets.append(SigBit(prioritized, priority_in.size() - 1));
-		}
-		std::optional<SigBit> set;
-		if (bit_sets.size()) {
-			if (bit_sets.size() == 1) {
-				set = bit_sets[0];
-			} else {
-				set = mod->addWire(NEW_ID);
-				// Polarities are consistent, as guaranteed by check prior
-				(*bit_set_pol ? mod->addReduceOr(NEW_ID, bit_sets, *set) : mod->addReduceAnd(NEW_ID, bit_sets, *set))->attributes = proc->attributes;
-			}
-		}
-		std::optional<SigBit> reset;
-		if (bit_resets.size()) {
-			if (bit_resets.size() == 1) {
-				reset = bit_resets[0];
-			} else {
-				reset = mod->addWire(NEW_ID);
-				(*bit_reset_pol ? mod->addReduceOr(NEW_ID, bit_resets, *reset) : mod->addReduceAnd(NEW_ID, bit_resets, *reset))->attributes = proc->attributes;
-			}
-		}
-		if (set)
-			sig_sr_set.append(*set);
-		else
-			sig_sr_set.append(*bit_set_pol ? Const(0, 1) : Const(1, 1));
-		if (reset)
-			sig_sr_clr.append(*reset);
-		else
-			sig_sr_clr.append(*bit_reset_pol ? Const(0, 1) : Const(1, 1));
+		auto [set, reset] = builder.build(bit_rules[i]);
+		sig_sr_set.append(*set);
+		sig_sr_clr.append(*reset);
 	}
-	priority->setPort(ID::A, priority_in);
-	priority->setParam(ID::POLARITY, priority_pol);
+	builder.finish(proc);
 
 	std::stringstream sstr;
 	sstr << "$procdff$" << (autoidx++);
 
 	RTLIL::Cell *cell = mod->addDffsr(sstr.str(), sigs.clk, sig_sr_set, sig_sr_clr, sigs.d, sigs.q, clk_polarity);
 	cell->attributes = proc->attributes;
-	priority->attributes = proc->attributes;
 
 	log("  created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
 			cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");

From 8cf422a823b622a718f57b05767e7fc4ab61f8a8 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 16 Jan 2026 23:46:38 +0100
Subject: [PATCH 9/9] proc_dff: fix missing polarity parameters for $dffsr, add
 another fallback

---
 passes/proc/proc_dff.cc | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index 998d18bca..0bd442e2e 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -169,8 +169,12 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 		}
 	}
 
-	log_assert(set_pol != std::nullopt);
-	log_assert(reset_pol != std::nullopt);
+	if (set_pol == std::nullopt || reset_pol == std::nullopt) {
+		// set or reset never used, falling back to mux tree
+		gen_dffsr_complex(mod, sigs, clk_polarity, async_rules, proc);
+		return;
+	}
+
 
 	struct Builder {
 		using BitControl = std::pair<std::optional<SigBit>, std::optional<SigBit>>;
@@ -280,6 +284,8 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
 
 	RTLIL::Cell *cell = mod->addDffsr(sstr.str(), sigs.clk, sig_sr_set, sig_sr_clr, sigs.d, sigs.q, clk_polarity);
 	cell->attributes = proc->attributes;
+	cell->setParam(ID::SET_POLARITY, Const(*set_pol, 1));
+	cell->setParam(ID::CLR_POLARITY, Const(*reset_pol, 1));
 
 	log("  created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
 			cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");