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https://github.com/YosysHQ/yosys
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Fixed techmap_wrap for techmap_celltype
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923bbbeaf0
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@ -363,6 +363,9 @@ struct TechmapWorker
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for (auto &c : cell->parameters)
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for (auto &c : cell->parameters)
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m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
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m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
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if (extmapper_name == "wrap")
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m_name += ":" + sha1(tpl->attributes.at("\\techmap_wrap").decode_string());
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RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
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RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
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RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
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RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
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@ -444,7 +447,6 @@ struct TechmapWorker
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break;
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break;
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}
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}
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use_wrapper_tpl:
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for (auto conn : cell->connections()) {
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for (auto conn : cell->connections()) {
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if (conn.first.substr(0, 1) == "$")
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if (conn.first.substr(0, 1) == "$")
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continue;
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continue;
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@ -511,16 +513,21 @@ struct TechmapWorker
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}
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}
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}
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}
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std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
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if (0) {
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if (techmap_cache.count(key) > 0) {
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use_wrapper_tpl:;
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tpl = techmap_cache[key];
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// do not register techmap_wrap modules with techmap_cache
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} else {
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} else {
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if (cell->parameters.size() != 0) {
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std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
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derived_name = tpl->derive(map, parameters);
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if (techmap_cache.count(key) > 0) {
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tpl = map->module(derived_name);
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tpl = techmap_cache[key];
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log_continue = true;
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} else {
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if (cell->parameters.size() != 0) {
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derived_name = tpl->derive(map, parameters);
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tpl = map->module(derived_name);
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log_continue = true;
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}
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techmap_cache[key] = tpl;
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}
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}
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techmap_cache[key] = tpl;
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}
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}
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if (flatten_mode) {
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if (flatten_mode) {
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