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xilinx: Add simulation model for DSP48 (Virtex 4).

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This commit is contained in:
Marcin Kościelnicki 2019-11-21 13:05:30 +01:00 • committed by Marcelina Kościelnicka
parent 7939727d14
commit 7e0e42f907
6 changed files with 534 additions and 45 deletions
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14
techlibs/xilinx/tests/test_dsp48_model.sh Normal file
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#!/bin/bash
set -ex
if [ -z $ISE_DIR ]; then
ISE_DIR=/opt/Xilinx/ISE/14.7
fi
sed 's/DSP48 /DSP48_UUT /; /DSP48_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp48_model_uut.v
if [ ! -f "test_dsp48_model_ref.v" ]; then
cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48.v test_dsp48_model_ref.v
fi
for tb in mult_allreg mult_noreg mult_inreg
do
iverilog -s $tb -s glbl -o test_dsp48_model test_dsp48_model.v test_dsp48_model_uut.v test_dsp48_model_ref.v $ISE_DIR/ISE_DS/ISE/verilog/src/glbl.v
vvp -N ./test_dsp48_model
done