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fix whitespace issues

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Rahul Bhagwat 2025-08-06 15:32:36 -04:00
parent fe59b6d3db
commit 7e0157ba2b
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2 changed files with 8 additions and 8 deletions
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4
tests/verilog/package_import_separate.sv
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@ -2,7 +2,7 @@ package config_pkg;
localparam integer
DATA_WIDTH = 8,
ADDR_WIDTH = 4;
localparam logic [2:0]
IDLE = 3'b000,
START = 3'b001,
@ -10,4 +10,4 @@ package config_pkg;
ODD_PARITY = 3'b011,
STOP = 3'b100,
DONE = 3'b101;
endpackage
endpackage