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Add mul_unsigned test

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This commit is contained in:
Eddie Hung 2019-08-30 14:35:05 -07:00
parent 89359b6927
commit 7df0e77565
2 changed files with 41 additions and 0 deletions
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tests/xilinx/mul_unsigned.ys Normal file
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read_verilog mul_unsigned.v
proc
hierarchy -top mul_unsigned
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_unsigned # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 15 t:SRL16E
select -assert-none t:DSP48E1 t:SRL16E t:BUFG %% t:* %D