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Fix issue with part of PI being 1'bx

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This commit is contained in:
Eddie Hung 2019-06-20 17:29:45 -07:00
parent d1dadfcec8
commit 7dca8def52
2 changed files with 11 additions and 4 deletions
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10
frontends/aiger/aigerparse.cc
View file

@ -944,11 +944,13 @@ void AigerReader::post_process()
if (other_wire) {
other_wire->port_input = false;
other_wire->port_output = false;
if (wire->port_input)
module->connect(other_wire, SigSpec(wire, i));
else
module->connect(SigSpec(wire, i), other_wire);
}
if (wire->port_input && other_wire)
module->connect(other_wire, SigSpec(wire, i));
else
// Since we skip POs that are connected to Sx,
// re-connect them here
module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx));
}
}

5
tests/simple_abc9/abc9.v
View file

@ -262,3 +262,8 @@ endmodule
module abc9_test025(input [3:0] i, output [3:0] o);
abc9_test024_sub a(i[2:1], o[2:1]);
endmodule
module abc9_test026(output [3:0] o, p);
assign o = { 1'b1, 1'bx };
assign p = { 1'b1, 1'bx, 1'b0 };
endmodule