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opt_boundary
This commit is contained in:
Akash Levy
parent
cd16928385
commit
7db8f29c04
4 changed files with 1204 additions and 0 deletions
851
tests/silimate/opt_boundary.ys
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851
tests/silimate/opt_boundary.ys
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###################################################################
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# Boundary optimization test cases
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###################################################################
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log -header "Copy simple child cone into parent"
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log -push
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design -reset
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read_verilog <<EOF
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module m(input a, input b, output y);
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assign y = a & b;
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endmodule
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module top(input a, input b, output y);
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m u(.a(a), .b(b), .y(y));
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endmodule
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EOF
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check -assert
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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design -save start
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flatten
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design -save gold
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design -load start
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opt_boundary
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opt_clean
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select -assert-count 1 top/t:$and
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select -assert-count 0 top/t:m
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flatten
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design -save gate
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design -reset
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design -copy-from gold -as gold A:top
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design -copy-from gate -as gate A:top
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rename -hide
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equiv_make gold gate equiv
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equiv_simple equiv
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equiv_status -assert equiv
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design -load gate
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opt_clean
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select -assert-count 1 top/t:$and
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select -assert-count 0 top/t:m
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design -reset
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log -pop
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log -header "Partially bypass multi-bit output when one bit cannot be copied"
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log -push
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design -reset
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read_verilog <<EOF
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module m(input clk, input a, input b, output [1:0] y);
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reg q;
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always @(posedge clk)
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q <= a;
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assign y[0] = a & b;
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assign y[1] = q;
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endmodule
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module top(input clk, input a, input b, output [1:0] y);
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m u(.clk(clk), .a(a), .b(b), .y(y));
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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design -save start
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flatten
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design -save gold
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design -load start
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opt_boundary
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opt_clean
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select -assert-count 1 top/t:m
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select -assert-count 1 top/t:$and
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flatten
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design -save gate
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design -reset
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design -copy-from gold -as gold A:top
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design -copy-from gate -as gate A:top
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rename -hide
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equiv_make gold gate equiv
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equiv_simple equiv
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equiv_status -assert equiv
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design -reset
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log -pop
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log -header "Ignore cone that depends on inout port"
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log -push
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design -reset
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read_verilog <<EOF
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module m(inout p, output y);
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assign y = p;
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endmodule
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module top(inout p, output y);
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m u(.p(p), .y(y));
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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opt_boundary
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opt_clean
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select -assert-count 1 top/t:m
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design -reset
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log -pop
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log -header "Leave memory read cone intact"
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log -push
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design -reset
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read_verilog <<EOF
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module m(input [1:0] addr, output y);
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reg [0:0] mem [0:3];
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assign y = mem[addr];
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endmodule
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module top(input [1:0] addr, output y);
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m u(.addr(addr), .y(y));
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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opt_boundary
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opt_clean
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select -assert-count 1 top/t:m
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design -reset
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log -pop
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log -header "Rollback failed copy leaves no parent temporaries"
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log -push
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design -reset
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read_verilog <<EOF
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module m(input a, input b, input c, input d, output y);
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assign y = ((a & b) ^ c) | d;
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endmodule
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module top(input a, input b, input c, input d, output y);
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m u(.a(a), .b(b), .c(c), .d(d), .y(y));
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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opt_boundary -max_cells 2
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select -assert-count 1 top/t:m
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select -assert-count 0 top/t:$and
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select -assert-count 0 top/t:$xor
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select -assert-count 0 top/t:$or
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check -assert
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design -reset
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log -pop
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log -header "Copy only mode leaves instance output connected"
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log -push
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design -reset
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read_verilog <<EOF
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module m(input a, input b, output y);
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assign y = a & b;
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endmodule
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module top(input a, input b, output y);
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m u(.a(a), .b(b), .y(y));
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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opt_boundary -no_disconnect
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select -assert-count 1 top/t:m
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select -assert-count 1 top/t:$and
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check -assert
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design -reset
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log -pop
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log -header "Bypass constant child output"
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log -push
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design -reset
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read_verilog <<EOF
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module m(output y);
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assign y = 1'b1;
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endmodule
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module top(output y);
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m u(.y(y));
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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design -save start
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flatten
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design -save gold
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design -load start
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opt_boundary
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opt_clean
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select -assert-count 0 top/t:m
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flatten
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design -save gate
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design -reset
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design -copy-from gold -as gold A:top
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design -copy-from gate -as gate A:top
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rename -hide
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equiv_make gold gate equiv
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equiv_simple equiv
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equiv_status -assert equiv
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design -reset
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log -pop
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log -header "Copy through sliced and concatenated port connections"
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log -push
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design -reset
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read_verilog <<EOF
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module m(input [3:0] i, output [1:0] y);
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assign y = {i[0] ^ i[3], i[1] & i[2]};
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endmodule
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module top(input [3:0] a, output [7:0] y);
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assign y[3:0] = a;
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assign y[7:6] = 2'b10;
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m u(.i({a[0], a[3], a[1], a[2]}), .y(y[5:4]));
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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design -save start
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flatten
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design -save gold
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design -load start
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opt_boundary
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opt_clean
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select -assert-count 0 top/t:m
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select -assert-count 1 top/t:$and
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select -assert-count 1 top/t:$xor
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flatten
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design -save gate
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design -reset
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design -copy-from gold -as gold A:top
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design -copy-from gate -as gate A:top
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rename -hide
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equiv_make gold gate equiv
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equiv_simple equiv
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equiv_status -assert equiv
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design -reset
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log -pop
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log -header "Copy shared internal cone feeding multiple outputs"
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log -push
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design -reset
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read_verilog <<EOF
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module m(input a, input b, input c, input d, output y, output z);
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wire t = a & b;
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assign y = t ^ c;
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assign z = t | d;
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endmodule
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module top(input a, input b, input c, input d, output y, output z);
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m u(.a(a), .b(b), .c(c), .d(d), .y(y), .z(z));
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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design -save start
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flatten
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design -save gold
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design -load start
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opt_boundary
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opt_clean
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select -assert-count 0 top/t:m
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select -assert-any top/t:$and
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select -assert-count 1 top/t:$xor
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select -assert-count 1 top/t:$or
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flatten
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design -save gate
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design -reset
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design -copy-from gold -as gold A:top
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design -copy-from gate -as gate A:top
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rename -hide
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equiv_make gold gate equiv
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equiv_simple equiv
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equiv_status -assert equiv
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design -reset
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log -pop
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log -header "Keep protected module boundary intact"
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log -push
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design -reset
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read_verilog <<EOF
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(* keep *)
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module m(input a, input b, output y);
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assign y = a & b;
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endmodule
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module top(input a, input b, output y);
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m u(.a(a), .b(b), .y(y));
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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opt_boundary
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opt_clean
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select -assert-count 1 top/t:m
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select -assert-count 0 top/t:$and
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design -reset
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log -pop
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log -header "Keep protected parent boundary intact"
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log -push
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design -reset
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read_verilog <<EOF
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module m(input a, input b, output y);
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assign y = a & b;
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endmodule
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(* keep *)
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module top(input a, input b, output y);
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m u(.a(a), .b(b), .y(y));
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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opt_boundary
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opt_clean
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select -assert-count 1 top/t:m
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select -assert-count 0 top/t:$and
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design -reset
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log -pop
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log -header "Only selected parent modules are optimized"
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log -push
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design -reset
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read_verilog <<EOF
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module m(input a, input b, output y);
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assign y = a & b;
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endmodule
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module top_keep(input a, input b, output y);
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m u(.a(a), .b(b), .y(y));
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endmodule
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module top_opt(input a, input b, output y);
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m u(.a(a), .b(b), .y(y));
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endmodule
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EOF
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proc
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opt_expr
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opt_clean
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opt_boundary top_opt
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opt_clean
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select -assert-count 1 top_keep/t:m
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select -assert-count 0 top_keep/t:$and
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select -assert-count 0 top_opt/t:m
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select -assert-count 1 top_opt/t:$and
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design -reset
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log -pop
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log -header "Copy cone from parameterized child module"
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log -push
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design -reset
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read_verilog <<EOF
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module m #(parameter WIDTH = 4) (input [WIDTH-1:0] a, input [WIDTH-1:0] b, output [WIDTH-1:0] y);
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assign y = a & b;
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endmodule
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module top(input [7:0] a, input [7:0] b, output [7:0] y);
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m #(.WIDTH(8)) u(.a(a), .b(b), .y(y));
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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design -save start
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flatten
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design -save gold
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design -load start
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opt_boundary
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opt_clean
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select -assert-count 0 top/t:m
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select -assert-any top/t:$and
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flatten
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design -save gate
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design -reset
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design -copy-from gold -as gold A:top
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design -copy-from gate -as gate A:top
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rename -hide
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equiv_make gold gate equiv
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equiv_simple equiv
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equiv_status -assert equiv
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design -reset
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log -pop
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log -header "Stress generated instances with vector cones"
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log -push
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design -reset
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read_verilog <<EOF
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module m(input [3:0] a, input [3:0] b, input [3:0] c, input [3:0] d, output [3:0] y);
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assign y = ((a & b) ^ c) | d;
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endmodule
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module top(input [31:0] a, input [31:0] b, input [31:0] c, input [31:0] d, output [31:0] y);
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genvar i;
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generate
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for (i = 0; i < 8; i = i + 1) begin : gen
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m u(
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.a(a[i*4 +: 4]),
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.b(b[i*4 +: 4]),
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.c(c[i*4 +: 4]),
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.d(d[i*4 +: 4]),
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.y(y[i*4 +: 4])
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);
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end
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endgenerate
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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design -save start
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flatten
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design -save gold
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design -load start
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opt_boundary -max_cells 3
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opt_clean
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select -assert-count 0 top/t:m
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select -assert-any top/t:$and
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select -assert-any top/t:$xor
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select -assert-any top/t:$or
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flatten
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design -save gate
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design -reset
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design -copy-from gold -as gold A:top
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design -copy-from gate -as gate A:top
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rename -hide
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equiv_make gold gate equiv
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equiv_simple equiv
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equiv_status -assert equiv
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design -reset
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log -pop
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log -header "Bypass direct child input to output"
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log -push
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design -reset
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read_verilog <<EOF
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module m(input a, output y);
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assign y = a;
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endmodule
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module top(input a, output y);
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m u(.a(a), .y(y));
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endmodule
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EOF
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hierarchy -top top
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proc
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opt_expr
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opt_clean
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design -save start
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flatten
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design -save gold
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design -load start
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opt_boundary
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opt_clean
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select -assert-count 0 top/t:m
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flatten
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design -save gate
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design -reset
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design -copy-from gold -as gold A:top
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design -copy-from gate -as gate A:top
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rename -hide
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equiv_make gold gate equiv
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equiv_simple equiv
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equiv_status -assert equiv
|
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design -reset
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log -pop
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log -header "Copy multi-bit vector cone"
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log -push
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design -reset
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read_verilog <<EOF
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module m(input [3:0] a, input [3:0] b, input [3:0] c, output [3:0] y);
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assign y = (a & b) ^ c;
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endmodule
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module top(input [3:0] a, input [3:0] b, input [3:0] c, output [3:0] y);
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m u(.a(a), .b(b), .c(c), .y(y));
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endmodule
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EOF
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hierarchy -top top
|
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proc
|
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opt_expr
|
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opt_clean
|
||||
design -save start
|
||||
flatten
|
||||
design -save gold
|
||||
design -load start
|
||||
opt_boundary
|
||||
opt_clean
|
||||
select -assert-count 0 top/t:m
|
||||
select -assert-any top/t:$and
|
||||
select -assert-any top/t:$xor
|
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flatten
|
||||
design -save gate
|
||||
|
||||
design -reset
|
||||
design -copy-from gold -as gold A:top
|
||||
design -copy-from gate -as gate A:top
|
||||
rename -hide
|
||||
equiv_make gold gate equiv
|
||||
equiv_simple equiv
|
||||
equiv_status -assert equiv
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Copy independent cones from two instances of one module type"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module m(input a, input b, output y);
|
||||
assign y = a & b;
|
||||
endmodule
|
||||
|
||||
module top(input a0, input b0, input a1, input b1, output y0, output y1);
|
||||
m u0(.a(a0), .b(b0), .y(y0));
|
||||
m u1(.a(a1), .b(b1), .y(y1));
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save start
|
||||
flatten
|
||||
design -save gold
|
||||
design -load start
|
||||
opt_boundary
|
||||
opt_clean
|
||||
select -assert-count 2 top/t:$and
|
||||
select -assert-count 0 top/t:m
|
||||
flatten
|
||||
design -save gate
|
||||
|
||||
design -reset
|
||||
design -copy-from gold -as gold A:top
|
||||
design -copy-from gate -as gate A:top
|
||||
rename -hide
|
||||
equiv_make gold gate equiv
|
||||
equiv_simple equiv
|
||||
equiv_status -assert equiv
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Honor max_cells limit"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module m(input a, input b, input c, input d, output y);
|
||||
assign y = ((a & b) ^ c) | d;
|
||||
endmodule
|
||||
|
||||
module top(input a, input b, input c, input d, output y);
|
||||
m u(.a(a), .b(b), .c(c), .d(d), .y(y));
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
opt_boundary -max_cells 2
|
||||
opt_clean
|
||||
select -assert-count 1 top/t:m
|
||||
select -assert-count 0 top/t:$and
|
||||
select -assert-count 0 top/t:$xor
|
||||
select -assert-count 0 top/t:$or
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Copy deeper cone when max_cells allows it"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module m(input a, input b, input c, input d, output y);
|
||||
assign y = ((a & b) ^ c) | d;
|
||||
endmodule
|
||||
|
||||
module top(input a, input b, input c, input d, output y);
|
||||
m u(.a(a), .b(b), .c(c), .d(d), .y(y));
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save start
|
||||
flatten
|
||||
design -save gold
|
||||
design -load start
|
||||
opt_boundary -max_cells 3
|
||||
opt_clean
|
||||
select -assert-count 0 top/t:m
|
||||
select -assert-count 1 top/t:$and
|
||||
select -assert-count 1 top/t:$xor
|
||||
select -assert-count 1 top/t:$or
|
||||
flatten
|
||||
design -save gate
|
||||
|
||||
design -reset
|
||||
design -copy-from gold -as gold A:top
|
||||
design -copy-from gate -as gate A:top
|
||||
rename -hide
|
||||
equiv_make gold gate equiv
|
||||
equiv_simple equiv
|
||||
equiv_status -assert equiv
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Leave blackbox boundary intact"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
(* blackbox *)
|
||||
module m(input a, input b, output y);
|
||||
endmodule
|
||||
|
||||
module top(input a, input b, output y);
|
||||
m u(.a(a), .b(b), .y(y));
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt_boundary
|
||||
opt_clean
|
||||
select -assert-count 1 top/t:m
|
||||
select -assert-count 0 top/t:$and
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Leave kept instance boundary intact"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module m(input a, input b, output y);
|
||||
assign y = a & b;
|
||||
endmodule
|
||||
|
||||
module top(input a, input b, output y);
|
||||
(* keep *) m u(.a(a), .b(b), .y(y));
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
opt_boundary
|
||||
opt_clean
|
||||
select -assert-count 1 top/t:m
|
||||
select -assert-count 0 top/t:$and
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Leave cone with kept internal cell intact"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -icells <<EOF
|
||||
module m(input a, input b, output y);
|
||||
(* keep *) \$and #(
|
||||
.A_SIGNED(1'b0),
|
||||
.B_SIGNED(1'b0),
|
||||
.A_WIDTH(1),
|
||||
.B_WIDTH(1),
|
||||
.Y_WIDTH(1)
|
||||
) kept_and (
|
||||
.A(a),
|
||||
.B(b),
|
||||
.Y(y)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module top(input a, input b, output y);
|
||||
m u(.a(a), .b(b), .y(y));
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt_boundary
|
||||
opt_clean
|
||||
select -assert-count 1 top/t:m
|
||||
select -assert-count 0 top/t:$and
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Leave cone with missing input connection intact"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module m(input a, input b, output y);
|
||||
assign y = a & b;
|
||||
endmodule
|
||||
|
||||
module top(input a, output y);
|
||||
m u(.a(a), .y(y));
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
opt_boundary
|
||||
opt_clean
|
||||
select -assert-count 1 top/t:m
|
||||
select -assert-count 0 top/t:$and
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Leave sequential cone intact"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module m(input clk, input d, output y);
|
||||
reg q;
|
||||
always @(posedge clk)
|
||||
q <= d;
|
||||
assign y = q & d;
|
||||
endmodule
|
||||
|
||||
module top(input clk, input d, output y);
|
||||
m u(.clk(clk), .d(d), .y(y));
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
opt_boundary
|
||||
opt_clean
|
||||
select -assert-count 1 top/t:m
|
||||
select -assert-count 0 top/t:$and
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Partially bypass one output while preserving live instance"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module m(input clk, input a, input b, output y, output q);
|
||||
reg q_r;
|
||||
always @(posedge clk)
|
||||
q_r <= a;
|
||||
assign q = q_r;
|
||||
assign y = a & b;
|
||||
endmodule
|
||||
|
||||
module top(input clk, input a, input b, output y, output q);
|
||||
m u(.clk(clk), .a(a), .b(b), .y(y), .q(q));
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save start
|
||||
flatten
|
||||
design -save gold
|
||||
design -load start
|
||||
opt_boundary
|
||||
opt_clean
|
||||
select -assert-count 1 top/t:m
|
||||
select -assert-count 1 top/t:$and
|
||||
flatten
|
||||
design -save gate
|
||||
|
||||
design -reset
|
||||
design -copy-from gold -as gold A:top
|
||||
design -copy-from gate -as gate A:top
|
||||
rename -hide
|
||||
equiv_make gold gate equiv
|
||||
equiv_simple equiv
|
||||
equiv_status -assert equiv
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Keep protected child boundary intact"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
(* keep_hierarchy *)
|
||||
module m(input a, input b, output y);
|
||||
assign y = a & b;
|
||||
endmodule
|
||||
|
||||
module top(input a, input b, output y);
|
||||
m u(.a(a), .b(b), .y(y));
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
check -assert
|
||||
|
||||
opt_boundary
|
||||
opt_clean
|
||||
select -assert-count 0 top/t:$and
|
||||
select -assert-count 1 top/t:m
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
61
tests/silimate/opt_boundary_random.tcl
Normal file
61
tests/silimate/opt_boundary_random.tcl
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
yosys -import
|
||||
|
||||
set tmp_v "opt_boundary_random_tmp.v"
|
||||
|
||||
proc emit_case {case_id width op0 op1 op2} {
|
||||
global tmp_v
|
||||
|
||||
set fh [open $tmp_v w]
|
||||
puts $fh "module m(input \[$width-1:0\] a, input \[$width-1:0\] b, input \[$width-1:0\] c, input \[$width-1:0\] d, output \[$width-1:0\] y);"
|
||||
puts $fh " wire \[$width-1:0\] t0 = a $op0 b;"
|
||||
puts $fh " wire \[$width-1:0\] t1 = t0 $op1 c;"
|
||||
puts $fh " assign y = t1 $op2 d;"
|
||||
puts $fh "endmodule"
|
||||
puts $fh ""
|
||||
puts $fh "module top(input \[$width-1:0\] a, input \[$width-1:0\] b, input \[$width-1:0\] c, input \[$width-1:0\] d, output \[$width-1:0\] y);"
|
||||
puts $fh " genvar i;"
|
||||
puts $fh " generate"
|
||||
puts $fh " for (i = 0; i < 4; i = i + 1) begin : gen"
|
||||
puts $fh " m u(.a({a\[$width-2:0\], a\[$width-1\]}), .b(b), .c(c), .d(d), .y(y));"
|
||||
puts $fh " end"
|
||||
puts $fh " endgenerate"
|
||||
puts $fh "endmodule"
|
||||
close $fh
|
||||
|
||||
log -header "randomized boundary case $case_id"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog $tmp_v
|
||||
hierarchy -top top
|
||||
yosys proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save start
|
||||
flatten
|
||||
design -save gold
|
||||
design -load start
|
||||
opt_boundary -max_cells 4
|
||||
opt_clean
|
||||
flatten
|
||||
design -save gate
|
||||
|
||||
design -reset
|
||||
design -copy-from gold -as gold A:top
|
||||
design -copy-from gate -as gate A:top
|
||||
yosys rename -hide
|
||||
equiv_make gold gate equiv
|
||||
equiv_simple equiv
|
||||
equiv_status -assert equiv
|
||||
log -pop
|
||||
}
|
||||
|
||||
set ops [list "&" "|" "^"]
|
||||
for {set i 0} {$i < 12} {incr i} {
|
||||
set width [expr {2 + ($i % 5)}]
|
||||
set op0 [lindex $ops [expr {$i % 3}]]
|
||||
set op1 [lindex $ops [expr {($i / 3) % 3}]]
|
||||
set op2 [lindex $ops [expr {($i / 9) % 3}]]
|
||||
emit_case $i $width $op0 $op1 $op2
|
||||
}
|
||||
|
||||
file delete -force $tmp_v
|
||||
Loading…
Add table
Add a link
Reference in a new issue