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Added verilog frontend -ignore_redef option

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This commit is contained in:
Clifford Wolf 2013-11-24 19:57:42 +01:00
parent 20175afd29
commit 7d9a90396d
3 changed files with 19 additions and 5 deletions
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11
frontends/ast/ast.cc
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@ -763,7 +763,7 @@ static AstModule* process_module(AstNode *ast)
}
// create AstModule instances for all modules in the AST tree and add them to 'design'
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt)
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool ignore_redef)
{
current_ast = ast;
flag_dump_ast1 = dump_ast1;
@ -777,9 +777,14 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
assert(current_ast->type == AST_DESIGN);
for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
if (design->modules.count((*it)->str) != 0)
log_error("Re-definition of module `%s' at %s:%d!\n",
if (design->modules.count((*it)->str) != 0) {
if (!ignore_redef)
log_error("Re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
log_error("Ignoring re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
continue;
}
design->modules[(*it)->str] = process_module(*it);
}
}