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allow attributes in front of ++/-- statements

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This commit is contained in:
Zachary Snow 2023-09-18 23:26:35 -04:00
parent 4edb1a1921
commit 7d07615dee
2 changed files with 15 additions and 15 deletions
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22
frontends/verilog/verilog_parser.y
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@ -301,14 +301,18 @@ static void ensureAsgnExprAllowed()
} }
// add a pre/post-increment/decrement statement // add a pre/post-increment/decrement statement
static const AstNode *addIncOrDecStmt(AstNode *lhs, dict<IdString, AstNode*> *attr, AST::AstNodeType op, YYLTYPE begin, YYLTYPE end) static const AstNode *addIncOrDecStmt(dict<IdString, AstNode*> *stmt_attr, AstNode *lhs,
dict<IdString, AstNode*> *op_attr, AST::AstNodeType op,
YYLTYPE begin, YYLTYPE end)
{ {
AstNode *one = AstNode::mkconst_int(1, true); AstNode *one = AstNode::mkconst_int(1, true);
AstNode *rhs = new AstNode(op, lhs->clone(), one); AstNode *rhs = new AstNode(op, lhs->clone(), one);
if (op_attr != nullptr)
append_attr(rhs, op_attr);
AstNode *stmt = new AstNode(AST_ASSIGN_EQ, lhs, rhs); AstNode *stmt = new AstNode(AST_ASSIGN_EQ, lhs, rhs);
SET_AST_NODE_LOC(stmt, begin, end); SET_AST_NODE_LOC(stmt, begin, end);
if (attr != nullptr) if (stmt_attr != nullptr)
append_attr(stmt, attr); append_attr(stmt, stmt_attr);
ast_stack.back()->children.push_back(stmt); ast_stack.back()->children.push_back(stmt);
return stmt; return stmt;
} }
@ -317,7 +321,7 @@ static const AstNode *addIncOrDecStmt(AstNode *lhs, dict<IdString, AstNode*> *at
static AstNode *addIncOrDecExpr(AstNode *lhs, dict<IdString, AstNode*> *attr, AST::AstNodeType op, YYLTYPE begin, YYLTYPE end, bool undo) static AstNode *addIncOrDecExpr(AstNode *lhs, dict<IdString, AstNode*> *attr, AST::AstNodeType op, YYLTYPE begin, YYLTYPE end, bool undo)
{ {
ensureAsgnExprAllowed(); ensureAsgnExprAllowed();
const AstNode *stmt = addIncOrDecStmt(lhs, attr, op, begin, end); const AstNode *stmt = addIncOrDecStmt(nullptr, lhs, attr, op, begin, end);
log_assert(stmt->type == AST_ASSIGN_EQ); log_assert(stmt->type == AST_ASSIGN_EQ);
AstNode *expr = stmt->children[0]->clone(); AstNode *expr = stmt->children[0]->clone();
if (undo) { if (undo) {
@ -2666,14 +2670,10 @@ simple_behavioral_stmt:
append_attr(node, $1); append_attr(node, $1);
} | } |
attr lvalue attr inc_or_dec_op { attr lvalue attr inc_or_dec_op {
// The position 1 attr to avoid shift/reduce conflicts with the addIncOrDecStmt($1, $2, $3, $4, @1, @4);
// other productions. We reject attributes in that position.
if (!$1->empty())
frontend_verilog_yyerror("Attributes are not allowed on this size of the lvalue in an inc_or_dec_expression!");
addIncOrDecStmt($2, $3, $4, @1, @4);
} | } |
inc_or_dec_op attr lvalue { attr inc_or_dec_op attr lvalue {
addIncOrDecStmt($3, $2, $1, @1, @3); addIncOrDecStmt($1, $4, $3, $2, @1, @4);
} | } |
attr lvalue OP_LE delay expr { attr lvalue OP_LE delay expr {
AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5); AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5);

8
tests/verilog/asgn_expr.sv
View file

@ -13,21 +13,21 @@ module top;
// post-increment/decrement statements // post-increment/decrement statements
x++; x++;
check(1, 0, 0); check(1, 0, 0);
y (* foo *) ++; (* bar *) y (* foo *) ++;
check(1, 1, 0); check(1, 1, 0);
z--; z--;
check(1, 1, -1); check(1, 1, -1);
z (* foo *) --; (* bar *) z (* foo *) --;
check(1, 1, -2); check(1, 1, -2);
// pre-increment/decrement statements are equivalent // pre-increment/decrement statements are equivalent
++z; ++z;
check(1, 1, -1); check(1, 1, -1);
++ (* foo *) z; (* bar *) ++ (* foo *) z;
check(1, 1, 0); check(1, 1, 0);
--x; --x;
check(0, 1, 0); check(0, 1, 0);
-- (* foo *) y; (* bar *) -- (* foo *) y;
check(0, 0, 0); check(0, 0, 0);
// procedural pre-increment/decrement expressions // procedural pre-increment/decrement expressions