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Fix integer signing grammar

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This commit fixes signed/unsigned grammar in parameters as defined in SV
LRM A2.2.1. Example of correct parameters:

parameter integer signed i = 0;
parameter integer unsigned i = 0;

Example of incorrect parameters:

parameter signed integer i = 0;
parameter unsigned integer i = 0;

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
This commit is contained in:
Lukasz Dalek 2020-05-18 21:01:16 +02:00 • committed by Kamil Rakoczy
parent 0835a86e30
commit 7cb56f34b0
1 changed files with 9 additions and 3 deletions
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12
frontends/verilog/verilog_parser.y
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@ -1329,6 +1329,8 @@ ignspec_id:
param_signed:
TOK_SIGNED {
astbuf1->is_signed = true;
} | TOK_UNSIGNED {
astbuf1->is_signed = false;
} | /* empty */;
param_integer:
@ -1339,14 +1341,14 @@ param_integer:
astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
astbuf1->is_signed = true;
} | /* empty */;
}
param_real:
TOK_REAL {
if (astbuf1->children.size() != 1)
frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
astbuf1->children.push_back(new AstNode(AST_REALVALUE));
} | /* empty */;
}
param_range:
range {
@ -1357,8 +1359,12 @@ param_range:
}
};
param_integer_type: param_integer param_signed
param_range_type: type_vec param_signed param_range
param_implicit_type: param_signed param_range
param_type:
param_signed param_integer param_real param_range |
param_integer_type | param_real | param_range_type | param_implicit_type |
hierarchical_type_id {
astbuf1->is_custom_type = true;
astbuf1->children.push_back(new AstNode(AST_WIRETYPE));