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https://github.com/YosysHQ/yosys
synced 2025-04-23 09:05:32 +00:00
Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32
This commit is contained in:
Clifford Wolf
parent
4569a747f8
commit
7cb0d3aa1a
5 changed files with 118 additions and 118 deletions
104
kernel/satgen.h
104
kernel/satgen.h
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@ -66,7 +66,7 @@ struct SatGen
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if (model_undef && dup_undef && bit == RTLIL::State::Sx)
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vec.push_back(ez->frozen_literal());
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else
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vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->TRUE : ez->FALSE);
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vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);
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} else {
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std::string name = pf + stringf(bit.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(bit.wire->name), bit.offset);
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vec.push_back(ez->frozen_literal(name));
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@ -160,9 +160,9 @@ struct SatGen
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if (!forced_signed && cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters.count("\\B_SIGNED") > 0)
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is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
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while (vec_a.size() < vec_b.size() || vec_a.size() < y_width)
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vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->FALSE);
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vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);
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while (vec_b.size() < vec_a.size() || vec_b.size() < y_width)
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vec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->FALSE);
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vec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->CONST_FALSE);
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}
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void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)
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@ -176,7 +176,7 @@ struct SatGen
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{
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bool is_signed = forced_signed || (cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool());
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while (vec_a.size() < vec_y.size())
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vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->FALSE);
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vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);
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while (vec_y.size() < vec_a.size())
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vec_y.push_back(ez->literal());
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}
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@ -226,7 +226,7 @@ struct SatGen
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if (is_arith_compare) {
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for (size_t i = 1; i < undef_y.size(); i++)
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ez->SET(ez->FALSE, undef_y.at(i));
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ez->SET(ez->CONST_FALSE, undef_y.at(i));
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ez->SET(undef_y_bit, undef_y.at(0));
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} else {
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std::vector<int> undef_y_bits(undef_y.size(), undef_y_bit);
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@ -307,7 +307,7 @@ struct SatGen
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int a = importDefSigSpec(cell->getPort("\\A"), timestep).at(0);
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int b = importDefSigSpec(cell->getPort("\\B"), timestep).at(0);
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int c = importDefSigSpec(cell->getPort("\\C"), timestep).at(0);
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int d = three_mode ? (aoi_mode ? ez->TRUE : ez->FALSE) : importDefSigSpec(cell->getPort("\\D"), timestep).at(0);
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int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort("\\D"), timestep).at(0);
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int y = importDefSigSpec(cell->getPort("\\Y"), timestep).at(0);
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int yy = model_undef ? ez->literal() : y;
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@ -321,7 +321,7 @@ struct SatGen
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int undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep).at(0);
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int undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep).at(0);
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int undef_c = importUndefSigSpec(cell->getPort("\\C"), timestep).at(0);
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int undef_d = three_mode ? ez->FALSE : importUndefSigSpec(cell->getPort("\\D"), timestep).at(0);
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int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort("\\D"), timestep).at(0);
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int undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep).at(0);
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if (aoi_mode)
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@ -433,14 +433,14 @@ struct SatGen
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std::vector<int> undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep);
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std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
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int maybe_one_hot = ez->FALSE;
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int maybe_many_hot = ez->FALSE;
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int maybe_one_hot = ez->CONST_FALSE;
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int maybe_many_hot = ez->CONST_FALSE;
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int sure_one_hot = ez->FALSE;
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int sure_many_hot = ez->FALSE;
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int sure_one_hot = ez->CONST_FALSE;
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int sure_many_hot = ez->CONST_FALSE;
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std::vector<int> bits_set = std::vector<int>(undef_y.size(), ez->FALSE);
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std::vector<int> bits_clr = std::vector<int>(undef_y.size(), ez->FALSE);
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std::vector<int> bits_set = std::vector<int>(undef_y.size(), ez->CONST_FALSE);
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std::vector<int> bits_clr = std::vector<int>(undef_y.size(), ez->CONST_FALSE);
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for (size_t i = 0; i < s.size(); i++)
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{
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@ -482,7 +482,7 @@ struct SatGen
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if (cell->type == "$pos") {
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ez->assume(ez->vec_eq(a, yy));
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} else {
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std::vector<int> zero(a.size(), ez->FALSE);
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std::vector<int> zero(a.size(), ez->CONST_FALSE);
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ez->assume(ez->vec_eq(ez->vec_sub(zero, a), yy));
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}
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@ -524,7 +524,7 @@ struct SatGen
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if (cell->type == "$logic_not")
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ez->SET(ez->NOT(ez->expression(ez->OpOr, a)), yy.at(0));
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for (size_t i = 1; i < y.size(); i++)
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ez->SET(ez->FALSE, yy.at(i));
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ez->SET(ez->CONST_FALSE, yy.at(i));
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if (model_undef)
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{
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@ -546,7 +546,7 @@ struct SatGen
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log_abort();
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for (size_t i = 1; i < undef_y.size(); i++)
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ez->SET(ez->FALSE, undef_y.at(i));
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ez->SET(ez->CONST_FALSE, undef_y.at(i));
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undefGating(y, yy, undef_y);
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}
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@ -569,7 +569,7 @@ struct SatGen
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else
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ez->SET(ez->expression(ez->OpOr, a, b), yy.at(0));
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for (size_t i = 1; i < y.size(); i++)
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ez->SET(ez->FALSE, yy.at(i));
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ez->SET(ez->CONST_FALSE, yy.at(i));
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if (model_undef)
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{
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@ -592,7 +592,7 @@ struct SatGen
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log_abort();
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for (size_t i = 1; i < undef_y.size(); i++)
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ez->SET(ez->FALSE, undef_y.at(i));
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ez->SET(ez->CONST_FALSE, undef_y.at(i));
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undefGating(y, yy, undef_y);
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}
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@ -630,7 +630,7 @@ struct SatGen
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if (cell->type == "$gt")
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ez->SET(is_signed ? ez->vec_gt_signed(a, b) : ez->vec_gt_unsigned(a, b), yy.at(0));
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for (size_t i = 1; i < y.size(); i++)
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ez->SET(ez->FALSE, yy.at(i));
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ez->SET(ez->CONST_FALSE, yy.at(i));
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if (model_undef && (cell->type == "$eqx" || cell->type == "$nex"))
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{
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@ -645,7 +645,7 @@ struct SatGen
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yy.at(0) = ez->OR(yy.at(0), ez->vec_ne(undef_a, undef_b));
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for (size_t i = 0; i < y.size(); i++)
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ez->SET(ez->FALSE, undef_y.at(i));
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ez->SET(ez->CONST_FALSE, undef_y.at(i));
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ez->assume(ez->vec_eq(y, yy));
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}
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@ -667,7 +667,7 @@ struct SatGen
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int undef_y_bit = ez->AND(undef_any, ez->NOT(masked_ne));
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for (size_t i = 1; i < undef_y.size(); i++)
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ez->SET(ez->FALSE, undef_y.at(i));
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ez->SET(ez->CONST_FALSE, undef_y.at(i));
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ez->SET(undef_y_bit, undef_y.at(0));
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undefGating(y, yy, undef_y);
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@ -689,7 +689,7 @@ struct SatGen
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std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
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std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
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int extend_bit = ez->FALSE;
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int extend_bit = ez->CONST_FALSE;
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if (!cell->type.in("$shift", "$shiftx") && cell->parameters["\\A_SIGNED"].as_bool())
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extend_bit = a.back();
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@ -703,16 +703,16 @@ struct SatGen
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std::vector<int> shifted_a;
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if (cell->type == "$shl" || cell->type == "$sshl")
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shifted_a = ez->vec_shift_left(a, b, false, ez->FALSE, ez->FALSE);
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shifted_a = ez->vec_shift_left(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
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if (cell->type == "$shr")
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shifted_a = ez->vec_shift_right(a, b, false, ez->FALSE, ez->FALSE);
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shifted_a = ez->vec_shift_right(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
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if (cell->type == "$sshr")
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shifted_a = ez->vec_shift_right(a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? a.back() : ez->FALSE, ez->FALSE);
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shifted_a = ez->vec_shift_right(a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
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if (cell->type == "$shift" || cell->type == "$shiftx")
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shifted_a = ez->vec_shift_right(a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->FALSE, ez->FALSE);
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shifted_a = ez->vec_shift_right(a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
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ez->assume(ez->vec_eq(shifted_a, yy));
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@ -723,7 +723,7 @@ struct SatGen
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std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
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std::vector<int> undef_a_shifted;
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extend_bit = cell->type == "$shiftx" ? ez->TRUE : ez->FALSE;
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extend_bit = cell->type == "$shiftx" ? ez->CONST_TRUE : ez->CONST_FALSE;
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if (!cell->type.in("$shift", "$shiftx") && cell->parameters["\\A_SIGNED"].as_bool())
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extend_bit = undef_a.back();
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@ -733,19 +733,19 @@ struct SatGen
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undef_a.push_back(extend_bit);
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if (cell->type == "$shl" || cell->type == "$sshl")
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undef_a_shifted = ez->vec_shift_left(undef_a, b, false, ez->FALSE, ez->FALSE);
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undef_a_shifted = ez->vec_shift_left(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
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if (cell->type == "$shr")
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undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->FALSE, ez->FALSE);
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undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
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if (cell->type == "$sshr")
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undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? undef_a.back() : ez->FALSE, ez->FALSE);
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undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
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if (cell->type == "$shift")
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undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->FALSE, ez->FALSE);
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undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
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if (cell->type == "$shiftx")
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undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->TRUE, ez->TRUE);
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undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE);
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int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
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std::vector<int> undef_all_y_bits(undef_y.size(), undef_any_b);
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@ -764,10 +764,10 @@ struct SatGen
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std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
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std::vector<int> tmp(a.size(), ez->FALSE);
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std::vector<int> tmp(a.size(), ez->CONST_FALSE);
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for (int i = 0; i < int(a.size()); i++)
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{
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std::vector<int> shifted_a(a.size(), ez->FALSE);
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std::vector<int> shifted_a(a.size(), ez->CONST_FALSE);
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for (int j = i; j < int(a.size()); j++)
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shifted_a.at(j) = a.at(j-i);
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tmp = ez->vec_ite(b.at(i), ez->vec_add(tmp, shifted_a), tmp);
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@ -791,7 +791,7 @@ struct SatGen
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Macc macc;
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macc.from_cell(cell);
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std::vector<int> tmp(GetSize(y), ez->FALSE);
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std::vector<int> tmp(GetSize(y), ez->CONST_FALSE);
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for (auto &port : macc.ports)
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{
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@ -799,17 +799,17 @@ struct SatGen
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std::vector<int> in_b = importDefSigSpec(port.in_b, timestep);
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while (GetSize(in_a) < GetSize(y))
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in_a.push_back(port.is_signed && !in_a.empty() ? in_a.back() : ez->FALSE);
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in_a.push_back(port.is_signed && !in_a.empty() ? in_a.back() : ez->CONST_FALSE);
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in_a.resize(GetSize(y));
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if (GetSize(in_b))
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{
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while (GetSize(in_b) < GetSize(y))
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in_b.push_back(port.is_signed && !in_b.empty() ? in_b.back() : ez->FALSE);
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in_b.push_back(port.is_signed && !in_b.empty() ? in_b.back() : ez->CONST_FALSE);
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in_b.resize(GetSize(y));
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for (int i = 0; i < GetSize(in_b); i++) {
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std::vector<int> shifted_a(in_a.size(), ez->FALSE);
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std::vector<int> shifted_a(in_a.size(), ez->CONST_FALSE);
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for (int j = i; j < int(in_a.size()); j++)
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shifted_a.at(j) = in_a.at(j-i);
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if (port.do_subtract)
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@ -828,7 +828,7 @@ struct SatGen
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}
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for (int i = 0; i < GetSize(b); i++) {
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std::vector<int> val(GetSize(y), ez->FALSE);
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std::vector<int> val(GetSize(y), ez->CONST_FALSE);
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val.at(0) = b.at(i);
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tmp = ez->vec_add(tmp, val);
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}
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@ -871,14 +871,14 @@ struct SatGen
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}
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std::vector<int> chain_buf = a_u;
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std::vector<int> y_u(a_u.size(), ez->FALSE);
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std::vector<int> y_u(a_u.size(), ez->CONST_FALSE);
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for (int i = int(a.size())-1; i >= 0; i--)
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{
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chain_buf.insert(chain_buf.end(), chain_buf.size(), ez->FALSE);
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chain_buf.insert(chain_buf.end(), chain_buf.size(), ez->CONST_FALSE);
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std::vector<int> b_shl(i, ez->FALSE);
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std::vector<int> b_shl(i, ez->CONST_FALSE);
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b_shl.insert(b_shl.end(), b_u.begin(), b_u.end());
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b_shl.insert(b_shl.end(), chain_buf.size()-b_shl.size(), ez->FALSE);
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b_shl.insert(b_shl.end(), chain_buf.size()-b_shl.size(), ez->CONST_FALSE);
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y_u.at(i) = ez->vec_ge_unsigned(chain_buf, b_shl);
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chain_buf = ez->vec_ite(y_u.at(i), ez->vec_sub(chain_buf, b_shl), chain_buf);
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@ -905,13 +905,13 @@ struct SatGen
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std::vector<int> div_zero_result;
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if (cell->type == "$div") {
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if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) {
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std::vector<int> all_ones(y.size(), ez->TRUE);
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std::vector<int> only_first_one(y.size(), ez->FALSE);
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only_first_one.at(0) = ez->TRUE;
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std::vector<int> all_ones(y.size(), ez->CONST_TRUE);
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std::vector<int> only_first_one(y.size(), ez->CONST_FALSE);
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only_first_one.at(0) = ez->CONST_TRUE;
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div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
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} else {
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div_zero_result.insert(div_zero_result.end(), cell->getPort("\\A").size(), ez->TRUE);
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div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
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div_zero_result.insert(div_zero_result.end(), cell->getPort("\\A").size(), ez->CONST_TRUE);
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div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
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}
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} else {
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int copy_a_bits = std::min(cell->getPort("\\A").size(), cell->getPort("\\B").size());
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@ -919,7 +919,7 @@ struct SatGen
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if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
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div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
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else
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div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
|
||||
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
|
||||
}
|
||||
ez->assume(ez->vec_eq(yy, ez->vec_ite(ez->expression(ezSAT::OpOr, b), y_tmp, div_zero_result)));
|
||||
}
|
||||
|
|
@ -939,15 +939,15 @@ struct SatGen
|
|||
|
||||
std::vector<int> lut;
|
||||
for (auto bit : cell->getParam("\\LUT").bits)
|
||||
lut.push_back(bit == RTLIL::S1 ? ez->TRUE : ez->FALSE);
|
||||
lut.push_back(bit == RTLIL::S1 ? ez->CONST_TRUE : ez->CONST_FALSE);
|
||||
while (GetSize(lut) < (1 << GetSize(a)))
|
||||
lut.push_back(ez->FALSE);
|
||||
lut.push_back(ez->CONST_FALSE);
|
||||
lut.resize(1 << GetSize(a));
|
||||
|
||||
if (model_undef)
|
||||
{
|
||||
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
|
||||
std::vector<int> t(lut), u(GetSize(t), ez->FALSE);
|
||||
std::vector<int> t(lut), u(GetSize(t), ez->CONST_FALSE);
|
||||
|
||||
for (int i = GetSize(a)-1; i >= 0; i--)
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue