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twine: fix replayability, reduce TwineSearch usage

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This commit is contained in:
Emil J. Tywoniak 2026-06-22 17:53:19 +02:00
parent e9eb3889b7
commit 7c73fd62e4
41 changed files with 273 additions and 272 deletions
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17
passes/techmap/extract.cc
View file

@ -294,14 +294,17 @@ RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit:
auto &tw = needle->design->twines;
// create new cell
RTLIL::Cell *cell = haystack->addCell(Twine{stringf("$extract$%s$%d", needle->name, autoidx++)}, Twine{needle->name.str()});
RTLIL::Cell *cell = haystack->addCell(haystack->design->twines.add(stringf("$extract$%s$%d", needle->name, autoidx++)), haystack->design->twines.add(needle->name.str()));
// create cell ports
// create cell ports. Port names come from the needle (map) pool; translate
// them into the haystack pool so the new cell's ports are keyed by the same
// refs as the referenced module in the haystack design.
for (auto wire : needle->wires()) {
if (wire->port_id > 0) {
TwineRef portname = haystack->design->twines.add(tw.str(wire->meta_->name));
for (int i = 0; i < wire->width; i++)
sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<TwineRef, int>(wire->meta_->name, i));
cell->setPort(wire->meta_->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<TwineRef, int>(portname, i));
cell->setPort(portname, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
}
}
@ -628,7 +631,7 @@ struct ExtractPass : public Pass {
if (!mine_mode)
for (auto module : map->modules()) {
SubCircuit::Graph mod_graph;
std::string graph_name = "needle_" + design->twines.unescaped_str(module->name);
std::string graph_name = "needle_" + map->twines.unescaped_str(module->name);
log("Creating needle graph %s.\n", graph_name);
if (module2graph(mod_graph, module, constports)) {
solver.addGraph(graph_name, mod_graph);
@ -656,8 +659,8 @@ struct ExtractPass : public Pass {
for (auto needle : needle_list)
for (auto &haystack_it : haystack_map) {
log("Solving for %s in %s.\n", ("needle_" + design->twines.unescaped_str(needle->name)), haystack_it.first);
solver.solve(results, "needle_" + design->twines.unescaped_str(needle->name), haystack_it.first, false);
log("Solving for %s in %s.\n", ("needle_" + map->twines.unescaped_str(needle->name)), haystack_it.first);
solver.solve(results, "needle_" + map->twines.unescaped_str(needle->name), haystack_it.first, false);
}
log("Found %d matches.\n", GetSize(results));

2
passes/techmap/muxcover.cc
View file

@ -170,7 +170,7 @@ struct MuxcoverWorker
return true;
}
char port_name[3] = {'\\', *path, 0};
return follow_muxtree(ret_bit, tree, sigmap(tree.muxes.at(bit)->getPort(tree.muxes.at(bit)->module->design->twines.add(Twine{std::string(port_name)}))), path+1, false);
return follow_muxtree(ret_bit, tree, sigmap(tree.muxes.at(bit)->getPort(tree.muxes.at(bit)->module->design->twines.add(std::string(port_name)))), path+1, false);
} else {
ret_bit = bit;
return true;

1
passes/techmap/techmap.cc
View file

@ -535,7 +535,6 @@ struct TechmapWorker
extmapper_module = extmapper_design->addModule(extmapper_design->twines.add(std::string{m_name}));
RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type.ref(), cell);
// addCell(name, cell) already migrated src across
// designs via copy_src_into — no need for an
// explicit set_src_attribute round-trip here.
int port_counter = 1;