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https://github.com/YosysHQ/yosys
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twine: fix replayability, reduce TwineSearch usage
This commit is contained in:
Emil J. Tywoniak
parent
e9eb3889b7
commit
7c73fd62e4
41 changed files with 273 additions and 272 deletions
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@ -953,7 +953,6 @@ bool RTLIL::AttrObject::get_bool_attribute(IdString id) const
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void RTLIL::AttrObject::set_string_attribute(IdString id, string value)
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{
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// ID::src on the base AttrObject is not routable here because the base
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// has no Design context — callers needing string-form src must go
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// through the subtype helper (Cell::set_src_attribute / Wire::… / …)
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// which derives the design from context.
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log_assert(id != ID::src && "set_string_attribute(ID::src,...) on AttrObject base; use the subtype helper");
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@ -965,7 +964,6 @@ void RTLIL::AttrObject::set_string_attribute(IdString id, string value)
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string RTLIL::AttrObject::get_string_attribute(IdString id) const
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{
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// ID::src is not in the dict — callers must use the subtype helper.
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log_assert(id != ID::src && "get_string_attribute(ID::src) on AttrObject base; use the subtype helper");
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std::string value;
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const auto it = attributes.find(id);
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@ -1821,22 +1819,22 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartial
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switch (boxes)
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{
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case RTLIL::SB_UNBOXED_WARN:
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log_warning("Ignoring boxed module %s.\n", twines.str(it.first).c_str());
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log_warning("Ignoring boxed module %s.\n", log_id(it.second));
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break;
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case RTLIL::SB_EXCL_BB_WARN:
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log_warning("Ignoring blackbox module %s.\n", twines.str(it.first).c_str());
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log_warning("Ignoring blackbox module %s.\n", log_id(it.second));
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break;
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case RTLIL::SB_UNBOXED_ERR:
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log_error("Unsupported boxed module %s.\n", twines.str(it.first).c_str());
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log_error("Unsupported boxed module %s.\n", log_id(it.second));
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break;
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case RTLIL::SB_EXCL_BB_ERR:
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log_error("Unsupported blackbox module %s.\n", twines.str(it.first).c_str());
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log_error("Unsupported blackbox module %s.\n", log_id(it.second));
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break;
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case RTLIL::SB_UNBOXED_CMDERR:
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log_cmd_error("Unsupported boxed module %s.\n", twines.str(it.first).c_str());
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log_cmd_error("Unsupported boxed module %s.\n", log_id(it.second));
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break;
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case RTLIL::SB_EXCL_BB_CMDERR:
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log_cmd_error("Unsupported blackbox module %s.\n", twines.str(it.first).c_str());
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log_cmd_error("Unsupported blackbox module %s.\n", log_id(it.second));
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break;
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default:
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break;
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@ -1845,13 +1843,13 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartial
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switch(partials)
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{
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case RTLIL::SELECT_WHOLE_WARN:
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log_warning("Ignoring partially selected module %s.\n", twines.str(it.first).c_str());
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log_warning("Ignoring partially selected module %s.\n", log_id(it.second));
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break;
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case RTLIL::SELECT_WHOLE_ERR:
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log_error("Unsupported partially selected module %s.\n", twines.str(it.first).c_str());
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log_error("Unsupported partially selected module %s.\n", log_id(it.second));
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break;
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case RTLIL::SELECT_WHOLE_CMDERR:
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log_cmd_error("Unsupported partially selected module %s.\n", twines.str(it.first).c_str());
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log_cmd_error("Unsupported partially selected module %s.\n", log_id(it.second));
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break;
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default:
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break;
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@ -1893,7 +1891,6 @@ RTLIL::Module::~Module()
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delete pr.second;
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for (auto binding : bindings_)
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delete binding;
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// Module's own src — release last so the pool stays valid for
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// inner releases above.
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if (design)
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design->obj_release_src(this);
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@ -3172,7 +3169,6 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons
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// Transfer src across designs. Both modules must be attached
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// to a design for the migration to happen; in the
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// detached-clone() scratch flow (equiv_make, etc.) src is
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// dropped here — those callers don't preserve src across the
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// temp clone by design.
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if (this->design && new_mod->design)
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copy_src_into(this, this->design, new_mod, new_mod->design);
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@ -3189,7 +3185,6 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons
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return;
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// Preserve name already set by addWire/addCell (in dst's pool).
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TwineRef saved_name = dst_obj->meta_ ? dst_obj->meta_->name : Twine::Null;
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// Recycle old meta slot (no field releases — name's retain lives on).
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if (dst_obj->meta_) {
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dst_obj->meta_->name = Twine::Null;
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dst_obj->meta_->src = Twine::Null;
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@ -3274,7 +3269,6 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons
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// TwinePool allocates slots sequentially as copy_src_into →
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// copy_from interns each wire's src, so the destination pool
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// ends up with leaves in the same order the frontend
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// originally interned them — that lets write_rtlil emit
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// byte-equal "@N" refs across single-module clones into an
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// existing destination design.
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// Re-intern each wire/cell name from the source design's pool into
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@ -3472,7 +3466,6 @@ void RTLIL::Module::add(RTLIL::Process *process)
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processes[process->meta_->name] = process;
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process->module = this;
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// Propagate module back-pointer to every CaseRule/SwitchRule in the
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// root case tree and every MemWriteAction in the sync rules — so the
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// per-Design src meta vector can be resolved from any inner-process
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// AttrObject via `module->design` after attach.
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process->root_case.setModuleRecursive(this);
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@ -3853,7 +3846,6 @@ RTLIL::Memory *RTLIL::Module::addMemory(TwineRef name, const RTLIL::Memory *othe
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mem->size = other->size;
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mem->attributes = other->attributes;
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{
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// Clone path drops src for now — caller responsible for migrating
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// src across the design boundary if needed. addMemory(name) is the
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// common case.
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(void)other;
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@ -6783,7 +6775,6 @@ RTLIL::CaseRule *RTLIL::CaseRule::clone() const
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new_caserule->compare = compare;
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new_caserule->actions = actions;
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new_caserule->attributes = attributes;
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// clone() drops src — CaseRule has no pool backpointer, so we can't
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// retain. The caller (Module::addProcess(name, other)) is responsible
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// for walking the cloned tree and migrating src via context.
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for (auto &it : switches)
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@ -6807,7 +6798,6 @@ RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
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RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
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new_switchrule->signal = signal;
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new_switchrule->attributes = attributes;
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// clone() drops src — see CaseRule::clone for rationale.
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for (auto &it : cases)
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new_switchrule->cases.push_back(it->clone());
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return new_switchrule;
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@ -6821,7 +6811,6 @@ RTLIL::SyncRule *RTLIL::SyncRule::clone() const
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new_syncrule->signal = signal;
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new_syncrule->actions = actions;
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new_syncrule->mem_write_actions = mem_write_actions;
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// Drop meta_idx_ on the cloned MemWriteActions — the integer was
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// copied by the vector assignment above without registering with
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// any pool; the caller is responsible for migrating src across the
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// clone via context (see Process::clone).
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@ -6974,7 +6963,6 @@ void RTLIL::Memory::absorb_attrs(dict<IdString, RTLIL::Const> &&buf)
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module->design->absorb_attrs(this, std::move(buf));
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}
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// CaseRule / SwitchRule / MemWriteAction src helpers — all delegate to
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// module->design->obj_* via the back-pointer added in the earlier commit.
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TwineRef RTLIL::CaseRule::src_id() const
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{
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