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change ql-bram-types pass to use mode parameter; clean up primitive libraries
This commit is contained in:
N. Engelhardt
Martin Povišer
parent
688455ef69
commit
7c0dbc8822
13 changed files with 74503 additions and 74255 deletions
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@ -56,43 +56,43 @@ module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
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(* force_downto *)
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wire [Y_WIDTH-1:0] S = {AA ^ BB};
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assign CO[Y_WIDTH-1:0] = C[Y_WIDTH:1];
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//assign CO[Y_WIDTH-1] = co;
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//assign CO[Y_WIDTH-1] = co;
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generate
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adder_carry intermediate_adder (
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.cin ( ),
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.cout (C[0]),
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.p (1'b0),
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.g (CI),
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.sumout ()
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);
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adder_carry intermediate_adder (
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.cin ( ),
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.cout (C[0]),
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.p (1'b0),
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.g (CI),
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.sumout ()
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);
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endgenerate
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genvar i;
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generate if (Y_WIDTH > 2) begin
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for (i = 0; i < Y_WIDTH-2; i = i + 1) begin:slice
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adder_carry my_adder (
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.cin(C[i]),
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.g(AA[i]),
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.p(S[i]),
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.cout(C[i+1]),
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.sumout(Y[i])
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.cin (C[i]),
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.g (AA[i]),
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.p (S[i]),
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.cout (C[i+1]),
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.sumout (Y[i])
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);
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end
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end
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end endgenerate
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generate
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adder_carry final_adder (
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.cin (C[Y_WIDTH-2]),
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.cout (),
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.p (1'b0),
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.g (1'b0),
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.sumout (co)
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);
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adder_carry final_adder (
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.cin (C[Y_WIDTH-2]),
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.cout (),
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.p (1'b0),
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.g (1'b0),
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.sumout (co)
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);
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endgenerate
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assign Y[Y_WIDTH-2] = S[Y_WIDTH-2] ^ co;
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assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2];
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assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2];
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assign Y[Y_WIDTH-1] = S[Y_WIDTH-1] ^ C[Y_WIDTH-1];
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assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1];
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assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1];
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assign X = S;
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endmodule
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@ -19,104 +19,104 @@
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`default_nettype none
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(* abc9_lut=1 *)
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module LUT1(output wire O, input wire I0);
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parameter [1:0] INIT = 0;
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assign O = I0 ? INIT[1] : INIT[0];
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specify
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(I0 => O) = 74;
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endspecify
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parameter [1:0] INIT = 0;
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assign O = I0 ? INIT[1] : INIT[0];
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specify
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(I0 => O) = 74;
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endspecify
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endmodule
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(* abc9_lut=2 *)
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module LUT2(output wire O, input wire I0, I1);
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parameter [3:0] INIT = 0;
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wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 116;
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(I1 => O) = 74;
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endspecify
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parameter [3:0] INIT = 0;
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wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 116;
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(I1 => O) = 74;
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endspecify
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endmodule
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(* abc9_lut=3 *)
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module LUT3(output wire O, input wire I0, I1, I2);
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parameter [7:0] INIT = 0;
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wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 162;
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(I1 => O) = 116;
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(I2 => O) = 174;
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endspecify
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parameter [7:0] INIT = 0;
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wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 162;
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(I1 => O) = 116;
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(I2 => O) = 174;
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endspecify
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endmodule
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(* abc9_lut=3 *)
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module LUT4(output wire O, input wire I0, I1, I2, I3);
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parameter [15:0] INIT = 0;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 201;
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(I1 => O) = 162;
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(I2 => O) = 116;
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(I3 => O) = 74;
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endspecify
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parameter [15:0] INIT = 0;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 201;
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(I1 => O) = 162;
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(I2 => O) = 116;
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(I3 => O) = 74;
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endspecify
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endmodule
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(* abc9_lut=3 *)
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module LUT5(output wire O, input wire I0, I1, I2, I3, I4);
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parameter [31:0] INIT = 0;
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wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 228;
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(I1 => O) = 189;
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(I2 => O) = 143;
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(I3 => O) = 100;
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(I4 => O) = 55;
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endspecify
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parameter [31:0] INIT = 0;
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wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 228;
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(I1 => O) = 189;
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(I2 => O) = 143;
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(I3 => O) = 100;
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(I4 => O) = 55;
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endspecify
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endmodule
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(* abc9_lut=5 *)
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module LUT6(output wire O, input wire I0, I1, I2, I3, I4, I5);
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parameter [63:0] INIT = 0;
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wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
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wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 251;
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(I1 => O) = 212;
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(I2 => O) = 166;
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(I3 => O) = 123;
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(I4 => O) = 77;
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(I5 => O) = 43;
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endspecify
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parameter [63:0] INIT = 0;
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wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
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wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 251;
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(I1 => O) = 212;
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(I2 => O) = 166;
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(I3 => O) = 123;
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(I4 => O) = 77;
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(I5 => O) = 43;
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module sh_dff(
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C
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);
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initial Q <= 1'b0;
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always @(posedge C)
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Q <= D;
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specify
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(posedge C => (Q +: D)) = 0;
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$setuphold(posedge C, D, 0, 0);
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endspecify
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initial Q = 1'b0;
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always @(posedge C)
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Q <= D;
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specify
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(posedge C => (Q +: D)) = 0;
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$setuphold(posedge C, D, 0, 0);
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endspecify
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endmodule
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@ -124,253 +124,253 @@ endmodule
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(* blackbox *)
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(* keep *)
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module adder_carry(
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output wire sumout,
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(* abc9_carry *)
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output wire cout,
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input wire p,
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input wire g,
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(* abc9_carry *)
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input wire cin
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output wire sumout,
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(* abc9_carry *)
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output wire cout,
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input wire p,
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input wire g,
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(* abc9_carry *)
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input wire cin
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);
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assign sumout = p ^ cin;
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assign cout = p ? cin : g;
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specify
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(p => sumout) = 35;
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(g => sumout) = 35;
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(cin => sumout) = 40;
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(p => cout) = 67;
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(g => cout) = 65;
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(cin => cout) = 69;
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endspecify
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assign sumout = p ^ cin;
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assign cout = p ? cin : g;
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specify
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(p => sumout) = 35;
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(g => sumout) = 35;
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(cin => sumout) = 40;
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(p => cout) = 67;
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(g => cout) = 65;
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(cin => cout) = 69;
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module dff(
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C
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);
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initial Q <= 1'b0;
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initial Q = 1'b0;
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always @(posedge C)
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Q <= D;
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always @(posedge C)
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Q <= D;
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specify
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(posedge C=>(Q+:D)) = 285;
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$setuphold(posedge C, D, 56, 0);
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endspecify
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specify
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(posedge C=>(Q+:D)) = 285;
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$setuphold(posedge C, D, 56, 0);
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module dffn(
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C
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);
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initial Q <= 1'b0;
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initial Q = 1'b0;
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always @(negedge C)
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Q <= D;
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specify
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(negedge C=>(Q+:D)) = 285;
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$setuphold(negedge C, D, 56, 0);
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endspecify
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always @(negedge C)
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Q <= D;
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specify
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(negedge C=>(Q+:D)) = 285;
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$setuphold(negedge C, D, 56, 0);
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module dffsre(
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C,
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input wire E,
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input wire R,
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input wire S
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C,
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input wire E,
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input wire R,
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input wire S
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);
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initial Q <= 1'b0;
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initial Q = 1'b0;
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always @(posedge C or negedge S or negedge R)
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if (!R)
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Q <= 1'b0;
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else if (!S)
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Q <= 1'b1;
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else if (E)
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Q <= D;
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always @(posedge C or negedge S or negedge R)
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if (!R)
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Q <= 1'b0;
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else if (!S)
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Q <= 1'b1;
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else if (E)
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Q <= D;
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specify
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(posedge C => (Q +: D)) = 280;
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(R => Q) = 0;
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(S => Q) = 0;
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$setuphold(posedge C, D, 56, 0);
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$setuphold(posedge C, E, 32, 0);
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$setuphold(posedge C, R, 0, 0);
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$setuphold(posedge C, S, 0, 0);
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$recrem(posedge R, posedge C, 0, 0);
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$recrem(posedge S, posedge C, 0, 0);
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endspecify
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specify
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(posedge C => (Q +: D)) = 280;
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(R => Q) = 0;
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(S => Q) = 0;
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$setuphold(posedge C, D, 56, 0);
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$setuphold(posedge C, E, 32, 0);
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$setuphold(posedge C, R, 0, 0);
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$setuphold(posedge C, S, 0, 0);
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$recrem(posedge R, posedge C, 0, 0);
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$recrem(posedge S, posedge C, 0, 0);
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module dffnsre(
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C,
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input wire E,
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input wire R,
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input wire S
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C,
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input wire E,
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input wire R,
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input wire S
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);
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initial Q <= 1'b0;
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initial Q = 1'b0;
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always @(negedge C or negedge S or negedge R)
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if (!R)
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Q <= 1'b0;
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else if (!S)
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Q <= 1'b1;
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else if (E)
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Q <= D;
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specify
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(negedge C => (Q +: D)) = 280;
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(R => Q) = 0;
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(S => Q) = 0;
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$setuphold(negedge C, D, 56, 0);
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$setuphold(negedge C, E, 32, 0);
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$setuphold(negedge C, R, 0, 0);
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$setuphold(negedge C, S, 0, 0);
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$recrem(posedge R, negedge C, 0, 0);
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$recrem(posedge S, negedge C, 0, 0);
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endspecify
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always @(negedge C or negedge S or negedge R)
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if (!R)
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Q <= 1'b0;
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else if (!S)
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Q <= 1'b1;
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else if (E)
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Q <= D;
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specify
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(negedge C => (Q +: D)) = 280;
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(R => Q) = 0;
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(S => Q) = 0;
|
||||
$setuphold(negedge C, D, 56, 0);
|
||||
$setuphold(negedge C, E, 32, 0);
|
||||
$setuphold(negedge C, R, 0, 0);
|
||||
$setuphold(negedge C, S, 0, 0);
|
||||
$recrem(posedge R, negedge C, 0, 0);
|
||||
$recrem(posedge S, negedge C, 0, 0);
|
||||
endspecify
|
||||
|
||||
endmodule
|
||||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module sdffsre(
|
||||
output reg Q,
|
||||
input wire D,
|
||||
(* clkbuf_sink *)
|
||||
input wire C,
|
||||
input wire E,
|
||||
input wire R,
|
||||
input wire S
|
||||
output reg Q,
|
||||
input wire D,
|
||||
(* clkbuf_sink *)
|
||||
input wire C,
|
||||
input wire E,
|
||||
input wire R,
|
||||
input wire S
|
||||
);
|
||||
initial Q <= 1'b0;
|
||||
initial Q = 1'b0;
|
||||
|
||||
always @(posedge C)
|
||||
if (!R)
|
||||
Q <= 1'b0;
|
||||
else if (!S)
|
||||
Q <= 1'b1;
|
||||
else if (E)
|
||||
Q <= D;
|
||||
|
||||
specify
|
||||
(posedge C => (Q +: D)) = 280;
|
||||
$setuphold(posedge C, D, 56, 0);
|
||||
$setuphold(posedge C, R, 32, 0);
|
||||
$setuphold(posedge C, S, 0, 0);
|
||||
$setuphold(posedge C, E, 0, 0);
|
||||
endspecify
|
||||
always @(posedge C)
|
||||
if (!R)
|
||||
Q <= 1'b0;
|
||||
else if (!S)
|
||||
Q <= 1'b1;
|
||||
else if (E)
|
||||
Q <= D;
|
||||
|
||||
specify
|
||||
(posedge C => (Q +: D)) = 280;
|
||||
$setuphold(posedge C, D, 56, 0);
|
||||
$setuphold(posedge C, R, 32, 0);
|
||||
$setuphold(posedge C, S, 0, 0);
|
||||
$setuphold(posedge C, E, 0, 0);
|
||||
endspecify
|
||||
|
||||
endmodule
|
||||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module sdffnsre(
|
||||
output reg Q,
|
||||
input wire D,
|
||||
(* clkbuf_sink *)
|
||||
input wire C,
|
||||
input wire E,
|
||||
input wire R,
|
||||
input wire S
|
||||
output reg Q,
|
||||
input wire D,
|
||||
(* clkbuf_sink *)
|
||||
input wire C,
|
||||
input wire E,
|
||||
input wire R,
|
||||
input wire S
|
||||
);
|
||||
initial Q <= 1'b0;
|
||||
initial Q = 1'b0;
|
||||
|
||||
always @(negedge C)
|
||||
if (!R)
|
||||
Q <= 1'b0;
|
||||
else if (!S)
|
||||
Q <= 1'b1;
|
||||
else if (E)
|
||||
Q <= D;
|
||||
|
||||
specify
|
||||
(negedge C => (Q +: D)) = 280;
|
||||
$setuphold(negedge C, D, 56, 0);
|
||||
$setuphold(negedge C, R, 32, 0);
|
||||
$setuphold(negedge C, S, 0, 0);
|
||||
$setuphold(negedge C, E, 0, 0);
|
||||
endspecify
|
||||
always @(negedge C)
|
||||
if (!R)
|
||||
Q <= 1'b0;
|
||||
else if (!S)
|
||||
Q <= 1'b1;
|
||||
else if (E)
|
||||
Q <= D;
|
||||
|
||||
specify
|
||||
(negedge C => (Q +: D)) = 280;
|
||||
$setuphold(negedge C, D, 56, 0);
|
||||
$setuphold(negedge C, R, 32, 0);
|
||||
$setuphold(negedge C, S, 0, 0);
|
||||
$setuphold(negedge C, E, 0, 0);
|
||||
endspecify
|
||||
|
||||
endmodule
|
||||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module latchsre (
|
||||
output reg Q,
|
||||
input wire S,
|
||||
input wire R,
|
||||
input wire D,
|
||||
input wire G,
|
||||
input wire E
|
||||
output reg Q,
|
||||
input wire S,
|
||||
input wire R,
|
||||
input wire D,
|
||||
input wire G,
|
||||
input wire E
|
||||
);
|
||||
initial Q <= 1'b0;
|
||||
initial Q = 1'b0;
|
||||
|
||||
always @*
|
||||
begin
|
||||
if (!R)
|
||||
Q <= 1'b0;
|
||||
else if (!S)
|
||||
Q <= 1'b1;
|
||||
else if (E && G)
|
||||
Q <= D;
|
||||
end
|
||||
|
||||
specify
|
||||
(posedge G => (Q +: D)) = 0;
|
||||
$setuphold(posedge G, D, 0, 0);
|
||||
$setuphold(posedge G, E, 0, 0);
|
||||
$setuphold(posedge G, R, 0, 0);
|
||||
$setuphold(posedge G, S, 0, 0);
|
||||
endspecify
|
||||
always @*
|
||||
begin
|
||||
if (!R)
|
||||
Q <= 1'b0;
|
||||
else if (!S)
|
||||
Q <= 1'b1;
|
||||
else if (E && G)
|
||||
Q <= D;
|
||||
end
|
||||
|
||||
specify
|
||||
(posedge G => (Q +: D)) = 0;
|
||||
$setuphold(posedge G, D, 0, 0);
|
||||
$setuphold(posedge G, E, 0, 0);
|
||||
$setuphold(posedge G, R, 0, 0);
|
||||
$setuphold(posedge G, S, 0, 0);
|
||||
endspecify
|
||||
|
||||
endmodule
|
||||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module latchnsre (
|
||||
output reg Q,
|
||||
input wire S,
|
||||
input wire R,
|
||||
input wire D,
|
||||
input wire G,
|
||||
input wire E
|
||||
output reg Q,
|
||||
input wire S,
|
||||
input wire R,
|
||||
input wire D,
|
||||
input wire G,
|
||||
input wire E
|
||||
);
|
||||
initial Q <= 1'b0;
|
||||
initial Q = 1'b0;
|
||||
|
||||
always @*
|
||||
begin
|
||||
if (!R)
|
||||
Q <= 1'b0;
|
||||
else if (!S)
|
||||
Q <= 1'b1;
|
||||
else if (E && !G)
|
||||
Q <= D;
|
||||
end
|
||||
|
||||
specify
|
||||
(negedge G => (Q +: D)) = 0;
|
||||
$setuphold(negedge G, D, 0, 0);
|
||||
$setuphold(negedge G, E, 0, 0);
|
||||
$setuphold(negedge G, R, 0, 0);
|
||||
$setuphold(negedge G, S, 0, 0);
|
||||
endspecify
|
||||
always @*
|
||||
begin
|
||||
if (!R)
|
||||
Q <= 1'b0;
|
||||
else if (!S)
|
||||
Q <= 1'b1;
|
||||
else if (E && !G)
|
||||
Q <= D;
|
||||
end
|
||||
|
||||
specify
|
||||
(negedge G => (Q +: D)) = 0;
|
||||
$setuphold(negedge G, D, 0, 0);
|
||||
$setuphold(negedge G, E, 0, 0);
|
||||
$setuphold(negedge G, R, 0, 0);
|
||||
$setuphold(negedge G, S, 0, 0);
|
||||
endspecify
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -16,116 +16,116 @@
|
|||
|
||||
// DFF, asynchronous set/reset, enable
|
||||
module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q);
|
||||
input C;
|
||||
input S;
|
||||
input R;
|
||||
input E;
|
||||
input D;
|
||||
output Q;
|
||||
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
|
||||
input C;
|
||||
input S;
|
||||
input R;
|
||||
input E;
|
||||
input D;
|
||||
output Q;
|
||||
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
|
||||
endmodule
|
||||
|
||||
module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q);
|
||||
input C;
|
||||
input S;
|
||||
input R;
|
||||
input E;
|
||||
input D;
|
||||
output Q;
|
||||
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
|
||||
input C;
|
||||
input S;
|
||||
input R;
|
||||
input E;
|
||||
input D;
|
||||
output Q;
|
||||
dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
|
||||
endmodule
|
||||
|
||||
// DFF, synchronous set or reset, enable
|
||||
module \$_SDFFE_PN0P_ (D, C, R, E, Q);
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
input E;
|
||||
output Q;
|
||||
sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1));
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
input E;
|
||||
output Q;
|
||||
sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1));
|
||||
endmodule
|
||||
|
||||
module \$_SDFFE_PN1P_ (D, C, R, E, Q);
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
input E;
|
||||
output Q;
|
||||
sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R));
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
input E;
|
||||
output Q;
|
||||
sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R));
|
||||
endmodule
|
||||
|
||||
module \$_SDFFE_NN0P_ (D, C, R, E, Q);
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
input E;
|
||||
output Q;
|
||||
sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1));
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
input E;
|
||||
output Q;
|
||||
sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1));
|
||||
endmodule
|
||||
|
||||
module \$_SDFFE_NN1P_ (D, C, R, E, Q);
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
input E;
|
||||
output Q;
|
||||
sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R));
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
input E;
|
||||
output Q;
|
||||
sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R));
|
||||
endmodule
|
||||
|
||||
// Latch, no set/reset, no enable
|
||||
module \$_DLATCH_P_ (input E, D, output Q);
|
||||
latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1));
|
||||
latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1));
|
||||
endmodule
|
||||
|
||||
module \$_DLATCH_N_ (input E, D, output Q);
|
||||
latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1));
|
||||
latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1));
|
||||
endmodule
|
||||
|
||||
// Latch with async set and reset and enable
|
||||
module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q);
|
||||
latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S));
|
||||
latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S));
|
||||
endmodule
|
||||
|
||||
module \$_DLATCHSR_NPP_ (input E, S, R, D, output Q);
|
||||
latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S));
|
||||
latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S));
|
||||
endmodule
|
||||
|
||||
module \$__SHREG_DFF_P_ (D, Q, C);
|
||||
input D;
|
||||
input C;
|
||||
output Q;
|
||||
input D;
|
||||
input C;
|
||||
output Q;
|
||||
|
||||
parameter DEPTH = 2;
|
||||
parameter DEPTH = 2;
|
||||
|
||||
reg [DEPTH-2:0] q;
|
||||
reg [DEPTH-2:0] q;
|
||||
|
||||
genvar i;
|
||||
generate for (i = 0; i < DEPTH; i = i + 1) begin: slice
|
||||
genvar i;
|
||||
generate for (i = 0; i < DEPTH; i = i + 1) begin: slice
|
||||
|
||||
// First in chain
|
||||
generate if (i == 0) begin
|
||||
sh_dff #() shreg_beg (
|
||||
.Q(q[i]),
|
||||
.D(D),
|
||||
.C(C)
|
||||
);
|
||||
end endgenerate
|
||||
// Middle in chain
|
||||
generate if (i > 0 && i != DEPTH-1) begin
|
||||
sh_dff #() shreg_mid (
|
||||
.Q(q[i]),
|
||||
.D(q[i-1]),
|
||||
.C(C)
|
||||
);
|
||||
end endgenerate
|
||||
// Last in chain
|
||||
generate if (i == DEPTH-1) begin
|
||||
sh_dff #() shreg_end (
|
||||
.Q(Q),
|
||||
.D(q[i-1]),
|
||||
.C(C)
|
||||
);
|
||||
end endgenerate
|
||||
// First in chain
|
||||
generate if (i == 0) begin
|
||||
sh_dff #() shreg_beg (
|
||||
.Q(q[i]),
|
||||
.D(D),
|
||||
.C(C)
|
||||
);
|
||||
end endgenerate
|
||||
// Middle in chain
|
||||
generate if (i > 0 && i != DEPTH-1) begin
|
||||
sh_dff #() shreg_mid (
|
||||
.Q(q[i]),
|
||||
.D(q[i-1]),
|
||||
.C(C)
|
||||
);
|
||||
end endgenerate
|
||||
// Last in chain
|
||||
generate if (i == DEPTH-1) begin
|
||||
sh_dff #() shreg_end (
|
||||
.Q(Q),
|
||||
.D(q[i-1]),
|
||||
.C(C)
|
||||
);
|
||||
end endgenerate
|
||||
end: slice
|
||||
endgenerate
|
||||
|
||||
|
|
|
|||
246
techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py
Normal file
246
techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py
Normal file
|
|
@ -0,0 +1,246 @@
|
|||
import sys
|
||||
from datetime import datetime, timezone
|
||||
|
||||
def generate(filename):
|
||||
with open(filename, "w") as f:
|
||||
f.write("// **AUTOGENERATED FILE** **DO NOT EDIT**\n")
|
||||
f.write(f"// Generated by {sys.argv[0]} at {datetime.now(timezone.utc)}\n")
|
||||
|
||||
f.write("`timescale 1ns /10ps\n")
|
||||
for a_width in [1,2,4,9,18,36]:
|
||||
for b_width in [1,2,4,9,18,36]:
|
||||
f.write(f"""
|
||||
module TDP36K_BRAM_A_X{a_width}_B_X{b_width}_nonsplit (
|
||||
RESET_ni,
|
||||
WEN_A1_i, WEN_B1_i,
|
||||
REN_A1_i, REN_B1_i,
|
||||
CLK_A1_i, CLK_B1_i,
|
||||
BE_A1_i, BE_B1_i,
|
||||
ADDR_A1_i, ADDR_B1_i,
|
||||
WDATA_A1_i, WDATA_B1_i,
|
||||
RDATA_A1_o, RDATA_B1_o,
|
||||
FLUSH1_i,
|
||||
WEN_A2_i, WEN_B2_i,
|
||||
REN_A2_i, REN_B2_i,
|
||||
CLK_A2_i, CLK_B2_i,
|
||||
BE_A2_i, BE_B2_i,
|
||||
ADDR_A2_i, ADDR_B2_i,
|
||||
WDATA_A2_i, WDATA_B2_i,
|
||||
RDATA_A2_o, RDATA_B2_o,
|
||||
FLUSH2_i
|
||||
);
|
||||
|
||||
parameter [80:0] MODE_BITS = 81'd0;
|
||||
|
||||
input wire RESET_ni;
|
||||
input wire WEN_A1_i, WEN_B1_i;
|
||||
input wire REN_A1_i, REN_B1_i;
|
||||
input wire WEN_A2_i, WEN_B2_i;
|
||||
input wire REN_A2_i, REN_B2_i;
|
||||
|
||||
(* clkbuf_sink *)
|
||||
input wire CLK_A1_i;
|
||||
(* clkbuf_sink *)
|
||||
input wire CLK_B1_i;
|
||||
(* clkbuf_sink *)
|
||||
input wire CLK_A2_i;
|
||||
(* clkbuf_sink *)
|
||||
input wire CLK_B2_i;
|
||||
|
||||
input wire [ 1:0] BE_A1_i, BE_B1_i;
|
||||
input wire [14:0] ADDR_A1_i, ADDR_B1_i;
|
||||
input wire [17:0] WDATA_A1_i, WDATA_B1_i;
|
||||
output wire [17:0] RDATA_A1_o, RDATA_B1_o;
|
||||
|
||||
input wire FLUSH1_i;
|
||||
|
||||
input wire [ 1:0] BE_A2_i, BE_B2_i;
|
||||
input wire [13:0] ADDR_A2_i, ADDR_B2_i;
|
||||
input wire [17:0] WDATA_A2_i, WDATA_B2_i;
|
||||
output wire [17:0] RDATA_A2_o, RDATA_B2_o;
|
||||
|
||||
input wire FLUSH2_i;
|
||||
|
||||
TDP36K #(.MODE_BITS(MODE_BITS)) bram (
|
||||
.RESET_ni (RESET_ni),
|
||||
.WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i),
|
||||
.REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i),
|
||||
.CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i),
|
||||
.BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i),
|
||||
.ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i),
|
||||
.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
|
||||
.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
|
||||
.FLUSH1_i (FLUSH1_i),
|
||||
.WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i),
|
||||
.REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i),
|
||||
.CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i),
|
||||
.BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i),
|
||||
.ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i),
|
||||
.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
|
||||
.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
|
||||
.FLUSH2_i (FLUSH2_i)
|
||||
);
|
||||
|
||||
`ifdef SDF_SIM
|
||||
specify
|
||||
(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
|
||||
(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
|
||||
(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
|
||||
(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
|
||||
(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
|
||||
(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
|
||||
(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
|
||||
(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
|
||||
$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
|
||||
$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
|
||||
$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
|
||||
$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
|
||||
$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
|
||||
$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
|
||||
$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
|
||||
$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
|
||||
$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
|
||||
$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
|
||||
$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
|
||||
$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
|
||||
$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
|
||||
$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
|
||||
$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
|
||||
$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
|
||||
$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
|
||||
$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
|
||||
$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
|
||||
endspecify
|
||||
`endif
|
||||
endmodule
|
||||
""")
|
||||
|
||||
for a1_width in [1,2,4,9,18]:
|
||||
for b1_width in [1,2,4,9,18]:
|
||||
for a2_width in [1,2,4,9,18]:
|
||||
for b2_width in [1,2,4,9,18]:
|
||||
f.write(f"""
|
||||
module TDP36K_BRAM_A1_X{a1_width}_B1_X{b1_width}_A2_X{a2_width}_B2_X{b2_width}_split (
|
||||
RESET_ni,
|
||||
WEN_A1_i, WEN_B1_i,
|
||||
REN_A1_i, REN_B1_i,
|
||||
CLK_A1_i, CLK_B1_i,
|
||||
BE_A1_i, BE_B1_i,
|
||||
ADDR_A1_i, ADDR_B1_i,
|
||||
WDATA_A1_i, WDATA_B1_i,
|
||||
RDATA_A1_o, RDATA_B1_o,
|
||||
FLUSH1_i,
|
||||
WEN_A2_i, WEN_B2_i,
|
||||
REN_A2_i, REN_B2_i,
|
||||
CLK_A2_i, CLK_B2_i,
|
||||
BE_A2_i, BE_B2_i,
|
||||
ADDR_A2_i, ADDR_B2_i,
|
||||
WDATA_A2_i, WDATA_B2_i,
|
||||
RDATA_A2_o, RDATA_B2_o,
|
||||
FLUSH2_i
|
||||
);
|
||||
|
||||
parameter [80:0] MODE_BITS = 81'd0;
|
||||
|
||||
input wire RESET_ni;
|
||||
input wire WEN_A1_i, WEN_B1_i;
|
||||
input wire REN_A1_i, REN_B1_i;
|
||||
input wire WEN_A2_i, WEN_B2_i;
|
||||
input wire REN_A2_i, REN_B2_i;
|
||||
|
||||
(* clkbuf_sink *)
|
||||
input wire CLK_A1_i;
|
||||
(* clkbuf_sink *)
|
||||
input wire CLK_B1_i;
|
||||
(* clkbuf_sink *)
|
||||
input wire CLK_A2_i;
|
||||
(* clkbuf_sink *)
|
||||
input wire CLK_B2_i;
|
||||
|
||||
input wire [ 1:0] BE_A1_i, BE_B1_i;
|
||||
input wire [14:0] ADDR_A1_i, ADDR_B1_i;
|
||||
input wire [17:0] WDATA_A1_i, WDATA_B1_i;
|
||||
output wire [17:0] RDATA_A1_o, RDATA_B1_o;
|
||||
|
||||
input wire FLUSH1_i;
|
||||
|
||||
input wire [ 1:0] BE_A2_i, BE_B2_i;
|
||||
input wire [13:0] ADDR_A2_i, ADDR_B2_i;
|
||||
input wire [17:0] WDATA_A2_i, WDATA_B2_i;
|
||||
output wire [17:0] RDATA_A2_o, RDATA_B2_o;
|
||||
|
||||
input wire FLUSH2_i;
|
||||
|
||||
TDP36K #(.MODE_BITS(MODE_BITS)) bram (
|
||||
.RESET_ni (RESET_ni),
|
||||
.WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i),
|
||||
.REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i),
|
||||
.CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i),
|
||||
.BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i),
|
||||
.ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i),
|
||||
.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
|
||||
.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
|
||||
.FLUSH1_i (FLUSH1_i),
|
||||
.WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i),
|
||||
.REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i),
|
||||
.CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i),
|
||||
.BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i),
|
||||
.ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i),
|
||||
.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
|
||||
.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
|
||||
.FLUSH2_i (FLUSH2_i)
|
||||
);
|
||||
|
||||
`ifdef SDF_SIM
|
||||
specify
|
||||
(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
|
||||
(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
|
||||
(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
|
||||
(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
|
||||
(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
|
||||
(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
|
||||
(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
|
||||
(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
|
||||
$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
|
||||
$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
|
||||
$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
|
||||
$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
|
||||
$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
|
||||
$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
|
||||
$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
|
||||
$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
|
||||
$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
|
||||
$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
|
||||
$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
|
||||
$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
|
||||
$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
|
||||
$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
|
||||
$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
|
||||
$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
|
||||
$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
|
||||
$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
|
||||
$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
|
||||
$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
|
||||
endspecify
|
||||
`endif
|
||||
endmodule
|
||||
""")
|
||||
|
||||
if __name__ == "__main__":
|
||||
filename = "bram_types_sim.v"
|
||||
if len(sys.argv) > 1:
|
||||
filename = sys.argv[1]
|
||||
generate(filename)
|
||||
Loading…
Add table
Add a link
Reference in a new issue