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examples/anlogic/ now also output the SVF file.

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This commit is contained in:
Kali Prasad 2019-03-06 09:51:11 +05:30
parent d03780c3f4
commit 7c03b0b082
6 changed files with 12 additions and 10 deletions
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10
examples/anlogic/demo.v
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@ -1,18 +1,18 @@
module demo (
input wire CLK_IN,
output wire R_LED
input wire CLK_IN,
output wire R_LED
);
parameter time1 = 30'd12_000_000;
reg led_state;
reg [29:0] count;
always @(posedge CLK_IN)begin
if(count == time1)begin
count<= 30'd0;
count<= 30'd0;
led_state <= ~led_state;
end
else
count <= count + 1'b1;
end
assign R_LED = led_state;
endmodule
endmodule