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https://github.com/YosysHQ/yosys
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Implemented proper handling of stub placeholder modules
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parent
98fcb5daa3
commit
7bfc7b61a8
7 changed files with 70 additions and 16 deletions
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@ -89,6 +89,9 @@ struct VerilogFrontend : public Frontend {
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log(" -nopp\n");
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log(" do not run the pre-processor\n");
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log("\n");
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log(" -lib\n");
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log(" only create empty placeholder modules\n");
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log("\n");
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}
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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@ -100,6 +103,7 @@ struct VerilogFrontend : public Frontend {
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bool flag_mem2reg = false;
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bool flag_ppdump = false;
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bool flag_nopp = false;
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bool flag_lib = false;
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frontend_verilog_yydebug = false;
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log_header("Executing Verilog-2005 frontend.\n");
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@ -144,6 +148,10 @@ struct VerilogFrontend : public Frontend {
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flag_nopp = true;
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continue;
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}
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if (arg == "-lib") {
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flag_lib = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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@ -173,7 +181,7 @@ struct VerilogFrontend : public Frontend {
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frontend_verilog_yyparse();
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frontend_verilog_yylex_destroy();
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AST::process(design, current_ast, flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg);
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AST::process(design, current_ast, flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib);
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if (!flag_nopp)
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fclose(fp);
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