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Implemented proper handling of stub placeholder modules

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This commit is contained in:
Clifford Wolf 2013-03-28 09:20:10 +01:00
parent 98fcb5daa3
commit 7bfc7b61a8
7 changed files with 70 additions and 16 deletions
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24
backends/verilog/verilog_backend.cc
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@ -923,6 +923,11 @@ struct VerilogBackend : public Backend {
log(" without this option all internal cells are converted to verilog\n");
log(" expressions.\n");
log("\n");
log(" -placeholders\n");
log(" usually modules with the 'placeholder' attribute are ignored. with\n");
log(" this option set only the modules with the 'placeholder' attribute\n");
log(" are written to the output file.\n");
log("\n");
}
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
@ -933,6 +938,8 @@ struct VerilogBackend : public Backend {
attr2comment = false;
noexpr = false;
bool placeholders = false;
reg_ct.clear();
reg_ct.setup_stdcells_mem();
reg_ct.cell_types.insert("$sr");
@ -958,16 +965,21 @@ struct VerilogBackend : public Backend {
noexpr = true;
continue;
}
if (arg == "-placeholders") {
placeholders = true;
continue;
}
break;
}
extra_args(f, filename, args, argidx);
for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
log("Dumping module `%s'.\n", it->first.c_str());
if (it != design->modules.begin())
fprintf(f, "\n");
dump_module(f, "", it->second);
}
for (auto it = design->modules.begin(); it != design->modules.end(); it++)
if ((it->second->attributes.count("\\placeholder") > 0) == placeholders) {
if (it != design->modules.begin())
fprintf(f, "\n");
log("Dumping module `%s'.\n", it->first.c_str());
dump_module(f, "", it->second);
}
reg_ct.clear();
}