mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-05 19:00:26 +00:00
Code Activity

Using log_assert() instead of assert()

Browse source
This commit is contained in:
Clifford Wolf 2014-07-28 11:08:55 +02:00
parent d86a25f145
commit 7bd2d1064f
52 changed files with 236 additions and 251 deletions
Download patch file Download diff file Expand all files Collapse all files

23
passes/memory/memory_collect.cc
View file

@ -22,7 +22,6 @@
#include <sstream>
#include <algorithm>
#include <stdlib.h>
#include <assert.h>
static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
{
@ -136,12 +135,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
mem->parameters["\\SIZE"] = RTLIL::Const(memory->size);
mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
assert(sig_wr_clk.size() == wr_ports);
assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const());
assert(sig_wr_addr.size() == wr_ports * addr_bits);
assert(sig_wr_data.size() == wr_ports * memory->width);
assert(sig_wr_en.size() == wr_ports * memory->width);
log_assert(sig_wr_clk.size() == wr_ports);
log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
log_assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const());
log_assert(sig_wr_addr.size() == wr_ports * addr_bits);
log_assert(sig_wr_data.size() == wr_ports * memory->width);
log_assert(sig_wr_en.size() == wr_ports * memory->width);
mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0);
@ -152,11 +151,11 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
mem->set("\\WR_DATA", sig_wr_data);
mem->set("\\WR_EN", sig_wr_en);
assert(sig_rd_clk.size() == rd_ports);
assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const());
assert(sig_rd_addr.size() == rd_ports * addr_bits);
assert(sig_rd_data.size() == rd_ports * memory->width);
log_assert(sig_rd_clk.size() == rd_ports);
log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
log_assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const());
log_assert(sig_rd_addr.size() == rd_ports * addr_bits);
log_assert(sig_rd_data.size() == rd_ports * memory->width);
mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports);
mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0);

1
passes/memory/memory_dff.cc
View file

@ -20,7 +20,6 @@
#include "kernel/register.h"
#include "kernel/log.h"
#include <stdlib.h>
#include <assert.h>
#include <sstream>
static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)

1
passes/memory/memory_map.cc
View file

@ -22,7 +22,6 @@
#include <sstream>
#include <set>
#include <stdlib.h>
#include <assert.h>
static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "")
{

1
passes/memory/memory_unpack.cc
View file

@ -22,7 +22,6 @@
#include <sstream>
#include <algorithm>
#include <stdlib.h>
#include <assert.h>
static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
{