mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-25 21:57:01 +00:00
Code Activity

Using log_assert() instead of assert()

Browse source
This commit is contained in:
Clifford Wolf 2014-07-28 11:08:55 +02:00
parent d86a25f145
commit 7bd2d1064f
52 changed files with 236 additions and 251 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/hierarchy/hierarchy.cc
View file

@ -98,7 +98,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
generate_port_decl_t d = decl;
d.portname = portname;
d.index = *indices.begin();
assert(!indices.empty());
log_assert(!indices.empty());
indices.erase(d.index);
ports[d.index-1] = d;
portwidths[d.portname] = std::max(portwidths[d.portname], 1);
@ -110,7 +110,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
portnames.erase(portname);
}
assert(indices.empty());
log_assert(indices.empty());
RTLIL::Module *mod = new RTLIL::Module;
mod->name = celltype;