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Using log_assert() instead of assert()

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This commit is contained in:
Clifford Wolf 2014-07-28 11:08:55 +02:00
parent d86a25f145
commit 7bd2d1064f
52 changed files with 236 additions and 251 deletions
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4
passes/hierarchy/hierarchy.cc
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@ -98,7 +98,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
generate_port_decl_t d = decl;
d.portname = portname;
d.index = *indices.begin();
assert(!indices.empty());
log_assert(!indices.empty());
indices.erase(d.index);
ports[d.index-1] = d;
portwidths[d.portname] = std::max(portwidths[d.portname], 1);
@ -110,7 +110,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
portnames.erase(portname);
}
assert(indices.empty());
log_assert(indices.empty());
RTLIL::Module *mod = new RTLIL::Module;
mod->name = celltype;

2
passes/hierarchy/submod.cc
View file

@ -171,7 +171,7 @@ struct SubmodWorker
for (auto &conn : new_cell->connections_)
for (auto &bit : conn.second)
if (bit.wire != NULL) {
assert(wire_flags.count(bit.wire) > 0);
log_assert(wire_flags.count(bit.wire) > 0);
bit.wire = wire_flags[bit.wire].new_wire;
}
log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());