mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

Using log_assert() instead of assert()

Browse source
This commit is contained in:
Clifford Wolf 2014-07-28 11:08:55 +02:00
parent d86a25f145
commit 7bd2d1064f
52 changed files with 236 additions and 251 deletions
Download patch file Download diff file Expand all files Collapse all files

13
kernel/sigtools.h
View file

@ -22,7 +22,6 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
#include <assert.h>
#include <set>
struct SigPool
@ -67,7 +66,7 @@ struct SigPool
void expand(RTLIL::SigSpec from, RTLIL::SigSpec to)
{
assert(SIZE(from) == SIZE(to));
log_assert(SIZE(from) == SIZE(to));
for (int i = 0; i < SIZE(from); i++) {
bitDef_t bit_from(from[i]), bit_to(to[i]);
if (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)
@ -304,11 +303,11 @@ struct SigMap
// internal helper function
void merge_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2)
{
assert(bit1.wire != NULL && bit2.wire != NULL);
log_assert(bit1.wire != NULL && bit2.wire != NULL);
shared_bit_data_t *bd1 = bits[bit1];
shared_bit_data_t *bd2 = bits[bit2];
assert(bd1 != NULL && bd2 != NULL);
log_assert(bd1 != NULL && bd2 != NULL);
if (bd1 == bd2)
return;
@ -333,8 +332,8 @@ struct SigMap
// internal helper function
void set_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2)
{
assert(bit1.wire != NULL);
assert(bits.count(bit1) > 0);
log_assert(bit1.wire != NULL);
log_assert(bits.count(bit1) > 0);
bits[bit1]->map_to = bit2;
}
@ -347,7 +346,7 @@ struct SigMap
void add(RTLIL::SigSpec from, RTLIL::SigSpec to)
{
assert(SIZE(from) == SIZE(to));
log_assert(SIZE(from) == SIZE(to));
for (int i = 0; i < SIZE(from); i++)
{