mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00
Code Activity

Using log_assert() instead of assert()

Browse source
This commit is contained in:
Clifford Wolf 2014-07-28 11:08:55 +02:00
parent d86a25f145
commit 7bd2d1064f
52 changed files with 236 additions and 251 deletions
Download patch file Download diff file Expand all files Collapse all files

5
backends/verilog/verilog_backend.cc
View file

@ -30,7 +30,6 @@
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/log.h"
#include <assert.h>
#include <string>
#include <sstream>
#include <set>
@ -161,7 +160,7 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset =
if (width == 32 && !no_decimal) {
int32_t val = 0;
for (int i = offset+width-1; i >= offset; i--) {
assert(i < (int)data.bits.size());
log_assert(i < (int)data.bits.size());
if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1)
goto dump_bits;
if (data.bits[i] == RTLIL::S1)
@ -175,7 +174,7 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset =
if (width == 0)
fprintf(f, "0");
for (int i = offset+width-1; i >= offset; i--) {
assert(i < (int)data.bits.size());
log_assert(i < (int)data.bits.size());
switch (data.bits[i]) {
case RTLIL::S0: fprintf(f, "0"); break;
case RTLIL::S1: fprintf(f, "1"); break;