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Move implementation to constmap and add test

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This commit is contained in:
Kelvin Chung 2025-03-26 11:52:55 +00:00
parent 1113c8c95a
commit 7bbdf6049a
4 changed files with 129 additions and 38 deletions
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31
tests/techmap/constmap.ys Normal file
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@ -0,0 +1,31 @@
read_verilog << EOT
module test();
wire [31:0] in;
wire [31:0] out;
assign out = in + 16;
endmodule
EOT
constmap -cell const_cell O value
select -assert-count 1 t:const_cell
select -assert-count 1 r:value=16
design -reset
read_verilog << EOT
module test();
wire [31:0] in;
wire [31:0] out1;
wire [31:0] out2;
assign out1 = in + 16;
assign out2 = in + 32;
endmodule
EOT
constmap -cell const_cell O value
select -assert-count 2 t:const_cell
select -assert-count 1 r:value=16
select -assert-count 1 r:value=32