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https://github.com/YosysHQ/yosys
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ff: twines
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parent
3a5f5c77bf
commit
7baf458ffe
2 changed files with 6 additions and 6 deletions
10
kernel/ff.cc
10
kernel/ff.cc
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@ -26,14 +26,14 @@ USING_YOSYS_NAMESPACE
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template<typename InputType, typename OutputType, typename = std::enable_if_t<std::is_base_of_v<FfTypeData, OutputType>>>
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void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
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Cell* cell = nullptr;
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IdString type;
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TwineRef type;
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constexpr bool have_cell = std::is_same_v<InputType, Cell*>;
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if constexpr (std::is_same_v<InputType, IdString>) {
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if constexpr (std::is_same_v<InputType, TwineRef>) {
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type = flop;
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} else {
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static_assert(std::is_same_v<InputType, Cell*>);
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cell = flop;
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type = flop->type;
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type = flop->type.ref();
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}
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if constexpr (have_cell) {
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info.sig_q = cell->getPort(TW::Q);
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@ -52,7 +52,7 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
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}
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std::string type_str = type.str();
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std::string type_str = TW::str(type);
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if (type.in(TW($anyinit), TW($ff), TW($dff), TW($dffe), TW($dffsr), TW($dffsre), TW($adff), TW($adffe), TW($aldff), TW($aldffe), TW($sdff), TW($sdffe), TW($sdffce), TW($dlatch), TW($adlatch), TW($dlatchsr), TW($sr))) {
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if (type.in(TW($anyinit), TW($ff))) {
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@ -331,7 +331,7 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
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}
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}
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FfTypeData::FfTypeData(IdString type) : FfTypeData()
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FfTypeData::FfTypeData(TwineRef type) : FfTypeData()
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{
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manufacture_info(type, *this, nullptr);
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}
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@ -80,7 +80,7 @@ YOSYS_NAMESPACE_BEGIN
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// - empty set [not a cell — will be emitted as a simple direct connection]
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struct FfTypeData {
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FfTypeData(IdString type);
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FfTypeData(TwineRef type);
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FfTypeData() {
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has_clk = false;
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has_gclk = false;
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