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xilinx: consider DSP48E1.ADREG

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This commit is contained in:
Eddie Hung 2020-03-04 12:04:02 -08:00
parent 512596760b
commit 7b543fdb0c
4 changed files with 8 additions and 5 deletions
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1
techlibs/xilinx/abc9_unmap.v
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@ -47,6 +47,7 @@ module $__ABC9_DSP48E1(
output [47:0] P,
output [47:0] PCOUT
);
parameter integer ADREG = 1;
parameter integer AREG = 1;
parameter integer BREG = 1;
parameter integer CREG = 1;