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xilinx: consider DSP48E1.ADREG

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This commit is contained in:
Eddie Hung 2020-03-04 12:04:02 -08:00
parent 512596760b
commit 7b543fdb0c
4 changed files with 8 additions and 5 deletions
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5
techlibs/xilinx/abc9_model.v
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@ -107,6 +107,7 @@ module $__ABC9_DSP48E1 (
output [47:0] P,
output [47:0] PCOUT
);
parameter integer ADREG = 1;
parameter integer AREG = 1;
parameter integer BREG = 1;
parameter integer CREG = 1;
@ -176,7 +177,7 @@ module $__ABC9_DSP48E1 (
// Identical comb delays to DSP48E1 in cells_sim.v
generate
if (PREG == 0 && MREG == 0 && AREG == 0)
if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0)
specify
($A *> P) = \A.P.comb ();
($A *> PCOUT) = \A.PCOUT.comb ();
@ -194,7 +195,7 @@ module $__ABC9_DSP48E1 (
($C *> PCOUT) = \C.PCOUT.comb ();
endspecify
if (PREG == 0 && MREG == 0 && DREG == 0)
if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0)
specify
($D *> P) = \D.P.comb ();
($D *> PCOUT) = \D.PCOUT.comb ();