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xilinx: consider DSP48E1.ADREG

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This commit is contained in:
Eddie Hung 2020-03-04 12:04:02 -08:00
parent 512596760b
commit 7b543fdb0c
4 changed files with 8 additions and 5 deletions
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1
techlibs/xilinx/abc9_map.v
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@ -772,6 +772,7 @@ module DSP48E1 (
.RSTP(RSTP)
);
$__ABC9_DSP48E1 #(
.ADREG(ADREG),
.AREG(AREG),
.BREG(BREG),
.CREG(CREG),