From 7b5202ac7911c89b3f039e65b492493570decae7 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Mon, 24 Feb 2025 10:19:54 -0800 Subject: [PATCH] Disable wire removal --- passes/silimate/obs_clean.cc | 99 ++++++++++++++++++++++-------------- 1 file changed, 60 insertions(+), 39 deletions(-) diff --git a/passes/silimate/obs_clean.cc b/passes/silimate/obs_clean.cc index 15ab8e205..c3e5c33cc 100644 --- a/passes/silimate/obs_clean.cc +++ b/passes/silimate/obs_clean.cc @@ -14,7 +14,7 @@ void sigCellDrivers(RTLIL::Module *module, SigMap &sigmap, dictoutput(portName)) { - sig2CellsInFanin[actual].insert(cell); + sig2CellsInFanin[sigmap(actual)].insert(cell); for (int i = 0; i < actual.size(); i++) { SigSpec bit_sig = actual.extract(i, 1); sig2CellsInFanin[sigmap(bit_sig)].insert(cell); @@ -106,7 +106,7 @@ void collectTransitiveFanin(RTLIL::SigSpec &sig, SigMap &sigmap, dict> &sig2CellsInFanin, - dict &lhsSig2RhsSig) + dict &lhsSig2RhsSig, bool unused_wires) { if (module->get_bool_attribute(ID::keep)) return; @@ -119,9 +119,11 @@ void observabilityClean(RTLIL::Module *module, SigMap &sigmap, dictport_output) && (!w->get_bool_attribute(ID::keep))) { continue; } - collectTransitiveFanin(po, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec); + RTLIL::SigSpec spo = sigmap(po); + collectTransitiveFanin(spo, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec); for (int i = 0; i < po.size(); i++) { SigSpec bit_sig = po.extract(i, 1); + bit_sig = sigmap(bit_sig); collectTransitiveFanin(bit_sig, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec); } } @@ -132,9 +134,11 @@ void observabilityClean(RTLIL::Module *module, SigMap &sigmap, dictport_output) && (!w->get_bool_attribute(ID::keep))) { continue; } - collectTransitiveFanin(po, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec); + RTLIL::SigSpec spo = sigmap(po); + collectTransitiveFanin(spo, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec); for (int i = 0; i < po.size(); i++) { SigSpec bit_sig = po.extract(i, 1); + bit_sig = sigmap(bit_sig); collectTransitiveFanin(bit_sig, sigmap, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec); } } @@ -142,20 +146,12 @@ void observabilityClean(RTLIL::Module *module, SigMap &sigmap, dict newConnections; for (auto it = module->connections().begin(); it != module->connections().end(); ++it) { RTLIL::SigSpec lhs = it->first; - RTLIL::SigSpec sigmaplhs = sigmap(lhs); - if (!sigmaplhs.is_fully_const()) { - lhs = sigmaplhs; - } - if (visitedSigSpec.count(lhs)) { + if (visitedSigSpec.count(sigmap(lhs))) { newConnections.push_back(*it); } else { for (int i = 0; i < lhs.size(); i++) { SigSpec bit_sig = lhs.extract(i, 1); - RTLIL::SigSpec sigmapbit_sig = sigmap(bit_sig); - // if (!sigmapbit_sig.is_fully_const()) { - bit_sig = sigmapbit_sig; - //} - if (visitedSigSpec.count(bit_sig)) { + if (visitedSigSpec.count(sigmap(bit_sig))) { newConnections.push_back(*it); break; } @@ -168,31 +164,33 @@ void observabilityClean(RTLIL::Module *module, SigMap &sigmap, dictconnect(conn); } - pool wiresToRemove; - for (auto wire : module->wires()) { - RTLIL::SigSpec sig = wire; - if (visitedSigSpec.count(sigmap(sig))) { - continue; - } - bool bitVisited = false; - for (int i = 0; i < sig.size(); i++) { - SigSpec bit_sig = sig.extract(i, 1); - if (visitedSigSpec.count(bit_sig)) { - bitVisited = true; - break; + if (unused_wires) { + pool wiresToRemove; + for (auto wire : module->wires()) { + RTLIL::SigSpec sig = wire; + if (visitedSigSpec.count(sigmap(sig))) { + continue; } + bool bitVisited = false; + for (int i = 0; i < sig.size(); i++) { + SigSpec bit_sig = sig.extract(i, 1); + if (visitedSigSpec.count(bit_sig)) { + bitVisited = true; + break; + } + } + if (bitVisited) + continue; + if (wire->port_id) { + continue; + } + if (wire->get_bool_attribute(ID::keep)) + continue; + wiresToRemove.insert(wire); } - if (bitVisited) - continue; - if (wire->port_id) { - continue; - } - if (wire->get_bool_attribute(ID::keep)) - continue; - wiresToRemove.insert(wire); - } - module->remove(wiresToRemove); + module->remove(wiresToRemove); + } std::set cellsToRemove; for (auto cell : module->cells()) { @@ -212,9 +210,31 @@ void observabilityClean(RTLIL::Module *module, SigMap &sigmap, dict, RTLIL::Design *design) override + void help() override { + log("\n"); + log(" obs_clean [options] [selection]\n"); + log("\n"); + log("This pass performs an obversability-based logic removal.\n"); + log("\n"); + log(" -wires\n"); + log(" Also removes dangling wires. This option prevents formal verifciation at this time.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + bool unused_wires = false; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-wires") { + unused_wires = true; + continue; + } + break; + } + extra_args(args, argidx, design); + if (design == nullptr) { log_error("No design object"); return; @@ -226,6 +246,7 @@ struct ObsClean : public ScriptPass { continue; if (module->has_memories_warn()) continue; + SigMap sigmap(module); // Precompute cell output sigspec to cell map dict> sig2CellsInFanin; @@ -236,7 +257,7 @@ struct ObsClean : public ScriptPass { dict> rhsSig2LhsSig; lhs2rhs_rhs2lhs(module, sigmap, rhsSig2LhsSig, lhsSig2RhsSig); // Actual cleanup - observabilityClean(module, sigmap, sig2CellsInFanin, lhsSig2RhsSig); + observabilityClean(module, sigmap, sig2CellsInFanin, lhsSig2RhsSig, unused_wires); } log("End obs_clean pass\n"); log_flush();