mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
Improve "sim" command
This commit is contained in:
Clifford Wolf
parent
75046aa531
commit
7b4f3f86c3
1 changed files with 272 additions and 54 deletions
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@ -24,8 +24,16 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SimShared
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{
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bool debug = false;
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bool hide_internal = true;
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};
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struct SimInstance
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{
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SimShared *shared;
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Module *module;
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Cell *instance;
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@ -38,12 +46,20 @@ struct SimInstance
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dict<SigBit, pool<Wire*>> upd_outports;
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pool<SigBit> dirty_bits;
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dict<SigBit, State> next_state_nets;
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pool<SimInstance*, hash_ptr_ops> dirty_children;
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dict<Wire*, int> vcd_netids;
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struct ff_state_t
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{
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State past_clock;
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Const past_d;
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};
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SimInstance(Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
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module(module), instance(instance), parent(parent), sigmap(module)
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dict<Cell*, ff_state_t> ff_database;
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dict<Wire*, pair<int, Const>> vcd_database;
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SimInstance(SimShared *shared, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
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shared(shared), module(module), instance(instance), parent(parent), sigmap(module)
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{
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if (parent) {
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log_assert(parent->children.count(instance) == 0);
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@ -78,7 +94,7 @@ struct SimInstance
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Module *mod = module->design->module(cell->type);
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if (mod != nullptr) {
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new SimInstance(mod, cell, this);
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dirty_children.insert(new SimInstance(shared, mod, cell, this));
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}
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for (auto &port : cell->connections()) {
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@ -86,8 +102,21 @@ struct SimInstance
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for (auto bit : sigmap(port.second))
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upd_cells[bit].insert(cell);
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}
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if (cell->type.in("$dff")) {
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ff_state_t ff;
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ff.past_clock = State::Sx;
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ff.past_d = Const(State::Sx, cell->getParam("\\WIDTH").as_int());
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ff_database[cell] = ff;
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}
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}
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}
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~SimInstance()
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{
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for (auto child : children)
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delete child.second;
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}
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IdString name() const
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{
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@ -109,17 +138,22 @@ struct SimInstance
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Const value;
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for (auto bit : sigmap(sig))
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if (state_nets.count(bit))
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if (bit.wire == nullptr)
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value.bits.push_back(bit.data);
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else if (state_nets.count(bit))
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value.bits.push_back(state_nets.at(bit));
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else
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value.bits.push_back(State::Sz);
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// log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
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if (shared->debug)
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log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
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return value;
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}
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void set_state(SigSpec sig, Const value)
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bool set_state(SigSpec sig, Const value)
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{
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bool did_something = false;
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sig = sigmap(sig);
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log_assert(GetSize(sig) == GetSize(value));
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@ -127,13 +161,19 @@ struct SimInstance
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if (state_nets.at(sig[i]) != value[i]) {
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state_nets.at(sig[i]) = value[i];
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dirty_bits.insert(sig[i]);
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did_something = true;
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}
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// log("[%s] set %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
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if (shared->debug)
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log("[%s] set %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
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return did_something;
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}
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void update_cell(Cell *cell)
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{
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if (ff_database.count(cell))
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return;
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if (children.count(cell))
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{
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auto child = children.at(cell);
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@ -142,13 +182,12 @@ struct SimInstance
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Const value = get_state(conn.second);
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child->set_state(child->module->wire(conn.first), value);
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}
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dirty_children.insert(child);
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return;
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}
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if (yosys_celltypes.cell_evaluable(cell->type))
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{
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// log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type));
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RTLIL::SigSpec sig_a, sig_b, sig_c, sig_d, sig_s, sig_y;
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bool has_a, has_b, has_c, has_d, has_s, has_y;
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@ -166,6 +205,9 @@ struct SimInstance
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if (has_s) sig_s = cell->getPort("\\S");
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if (has_y) sig_y = cell->getPort("\\Y");
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if (shared->debug)
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log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type));
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// Simple (A -> Y) and (A,B -> Y) cells
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if (has_a && !has_c && !has_d && !has_s && has_y) {
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set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b)));
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@ -193,50 +235,113 @@ struct SimInstance
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log_warning("Unsupported cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
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}
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void update()
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void update_ph1()
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{
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pool<Cell*> queue_cells;
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pool<Wire*> queue_outports;
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while (1)
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{
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while (!dirty_bits.empty())
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for (auto bit : dirty_bits)
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{
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SigBit bit = *dirty_bits.begin();
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dirty_bits.erase(bit);
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if (upd_cells.count(bit))
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{
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for (auto cell : upd_cells.at(bit))
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update_cell(cell);
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}
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queue_cells.insert(cell);
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if (upd_outports.count(bit) && parent != nullptr)
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{
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for (auto wire : upd_outports.at(bit))
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queue_outports.insert(wire);
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}
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dirty_bits.clear();
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if (!queue_cells.empty())
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{
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for (auto cell : queue_cells)
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update_cell(cell);
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queue_cells.clear();
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continue;
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}
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for (auto wire : queue_outports)
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if (instance->hasPort(wire->name)) {
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Const value = get_state(wire);
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parent->set_state(instance->getPort(wire->name), value);
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}
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}
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}
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for (auto child : children)
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child.second->update();
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queue_outports.clear();
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for (auto child : dirty_children)
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child->update_ph1();
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dirty_children.clear();
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if (dirty_bits.empty())
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break;
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}
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}
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bool update_ph2()
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{
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bool did_something = false;
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for (auto &it : ff_database)
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{
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Cell *cell = it.first;
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ff_state_t &ff = it.second;
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if (cell->type.in("$dff"))
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{
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bool clkpol = cell->getParam("\\CLK_POLARITY").as_bool();
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State current_clock = get_state(cell->getPort("\\CLK"))[0];
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if (clkpol ? (ff.past_clock == State::S1 || current_clock != State::S1) :
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(ff.past_clock == State::S0 || current_clock != State::S0))
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continue;
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if (set_state(cell->getPort("\\Q"), ff.past_d))
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did_something = true;
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}
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}
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for (auto it : children)
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if (it.second->update_ph2()) {
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dirty_children.insert(it.second);
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did_something = true;
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}
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return did_something;
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}
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void update_ph3()
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{
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for (auto &it : ff_database)
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{
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Cell *cell = it.first;
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ff_state_t &ff = it.second;
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if (cell->type.in("$dff")) {
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ff.past_clock = get_state(cell->getPort("\\CLK"))[0];
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ff.past_d = get_state(cell->getPort("\\D"));
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}
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}
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for (auto it : children)
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it.second->update_ph3();
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}
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void write_vcd_header(std::ofstream &f, int &id)
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{
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f << stringf("$scope module %s $end\n", log_id(name()));
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for (auto wire : module->wires())
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{
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if (wire->name[0] == '$')
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if (shared->hide_internal && wire->name[0] == '$')
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continue;
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f << stringf("$var wire %d n%d %s $end\n", GetSize(wire), id, log_id(wire));
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vcd_netids[wire] = id++;
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f << stringf("$var wire %d n%d %s%s $end\n", GetSize(wire), id, wire->name[0] == '$' ? "\\" : "", log_id(wire));
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vcd_database[wire] = make_pair(id++, Const());
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}
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for (auto child : children)
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@ -247,11 +352,16 @@ struct SimInstance
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void write_vcd_step(std::ofstream &f)
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{
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for (auto it : vcd_netids)
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for (auto &it : vcd_database)
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{
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Wire *wire = it.first;
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Const value = get_state(wire);
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int id = it.second;
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int id = it.second.first;
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if (it.second.second == value)
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continue;
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it.second.second = value;
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f << "b";
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for (int i = GetSize(value)-1; i >= 0; i--) {
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@ -271,20 +381,15 @@ struct SimInstance
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}
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};
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struct SimWorker
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struct SimWorker : SimShared
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{
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SimInstance *top = nullptr;
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std::ofstream vcdfile;
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pool<IdString> clock, clockn, reset, resetn;
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void initialize(Module *topmod)
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~SimWorker()
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{
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top = new SimInstance(topmod);
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top->update();
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}
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void step()
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{
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// FIXME
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delete top;
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}
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void write_vcd_header()
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@ -298,14 +403,92 @@ struct SimWorker
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vcdfile << stringf("$enddefinitions $end\n");
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}
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void write_vcd_step(int n)
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void write_vcd_step(int t)
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{
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if (!vcdfile.is_open())
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return;
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vcdfile << stringf("#%d\n", 10*n);
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vcdfile << stringf("#%d\n", t);
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top->write_vcd_step(vcdfile);
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}
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void update()
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{
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do
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{
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if (debug)
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log("\n-- ph1 --\n");
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top->update_ph1();
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if (debug)
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log("\n-- ph2 --\n");
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}
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while (top->update_ph2());
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if (debug)
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log("\n-- ph3 --\n");
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top->update_ph3();
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}
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void set_inports(pool<IdString> ports, State value)
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{
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for (auto portname : ports)
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{
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Wire *w = top->module->wire(portname);
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if (w == nullptr)
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log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
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top->set_state(w, value);
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}
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}
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void run(Module *topmod, int numcycles)
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{
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log_assert(top == nullptr);
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top = new SimInstance(this, topmod);
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if (debug)
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log("\n===== 0 =====\n");
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set_inports(reset, State::S1);
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set_inports(resetn, State::S0);
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update();
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write_vcd_header();
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write_vcd_step(0);
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for (int cycle = 0; cycle < numcycles; cycle++)
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{
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if (debug)
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log("\n===== %d =====\n", 10*cycle + 5);
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set_inports(clock, State::S0);
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set_inports(clockn, State::S1);
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update();
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write_vcd_step(10*cycle + 5);
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if (debug)
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log("\n===== %d =====\n", 10*cycle + 10);
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set_inports(clock, State::S1);
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set_inports(clockn, State::S0);
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if (cycle == 0) {
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set_inports(reset, State::S0);
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set_inports(resetn, State::S1);
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}
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update();
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write_vcd_step(10*cycle + 10);
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}
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write_vcd_step(10*numcycles + 2);
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}
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};
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struct SimPass : public Pass {
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@ -321,14 +504,32 @@ struct SimPass : public Pass {
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log(" -vcd <filename>\n");
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log(" write the simulation results to the given VCD file\n");
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log("\n");
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log(" -clock <portname>\n");
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log(" name of top-level clock input\n");
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log("\n");
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log(" -clockn <portname>\n");
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log(" name of top-level clock input (inverse polarity)\n");
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log("\n");
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log(" -reset <portname>\n");
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log(" name of top-level reset input (active high)\n");
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log("\n");
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log(" -resetn <portname>\n");
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log(" name of top-level inverted reset input (active low)\n");
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log("\n");
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log(" -n <integer>\n");
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log(" number of steps to simulate (default: 20)\n");
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log(" number of cycles to simulate (default: 20)\n");
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log("\n");
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log(" -a\n");
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log(" include all nets in VCD output, nut just those with public names\n");
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log("\n");
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log(" -d\n");
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log(" enable debug output\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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SimWorker worker;
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int numsteps = 20;
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int numcycles = 20;
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log_header(design, "Executing SIM pass (simulate the circuit).\n");
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@ -339,7 +540,31 @@ struct SimPass : public Pass {
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continue;
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}
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if (args[argidx] == "-n" && argidx+1 < args.size()) {
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numsteps = atoi(args[++argidx].c_str());
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numcycles = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-clock" && argidx+1 < args.size()) {
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worker.clock.insert(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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if (args[argidx] == "-clockn" && argidx+1 < args.size()) {
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worker.clockn.insert(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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if (args[argidx] == "-reset" && argidx+1 < args.size()) {
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worker.reset.insert(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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if (args[argidx] == "-resetn" && argidx+1 < args.size()) {
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worker.resetn.insert(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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if (args[argidx] == "-a") {
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worker.hide_internal = false;
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continue;
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}
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if (args[argidx] == "-d") {
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worker.debug = true;
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continue;
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}
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break;
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@ -357,14 +582,7 @@ struct SimPass : public Pass {
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top_mod = mods.front();
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}
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worker.initialize(top_mod);
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worker.write_vcd_header();
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worker.write_vcd_step(0);
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for (int i = 1; i < numsteps; i++) {
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worker.step();
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worker.write_vcd_step(i);
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}
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worker.run(top_mod, numcycles);
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}
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} SimPass;
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