From 68a9c31d2a0f684cc75de32a4d6325a138a458b8 Mon Sep 17 00:00:00 2001
From: Dhaval Chaudhari <dhavalchaudhari39@gmail.com>
Date: Fri, 2 Jan 2026 17:47:19 +0530
Subject: [PATCH 1/3] verific: add support for relaxed checking option in
 VerificPass

---
 frontends/verific/verific.cc | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 5790e92f0..eb6893ef1 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -3688,6 +3688,10 @@ struct VerificPass : public Pass {
 				veri_file::AddLOption(args[++argidx].c_str());
 				continue;
 			}
+			if (args[argidx] == "-set_relaxed_checking") {
+				veri_file::SetRelaxedChecking(0);
+				continue;
+			}
 #endif
 			break;
 		}

From 0491177fe358dff06ebedc3a8a512701c35bdb57 Mon Sep 17 00:00:00 2001
From: Dhaval Chaudhari <dhavalchaudhari39@gmail.com>
Date: Fri, 2 Jan 2026 17:58:35 +0530
Subject: [PATCH 2/3] verific: add support for setting file extension modes in
 VerificPass

---
 frontends/verific/verific.cc | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index eb6893ef1..20720872b 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -3688,8 +3688,16 @@ struct VerificPass : public Pass {
 				veri_file::AddLOption(args[++argidx].c_str());
 				continue;
 			}
-			if (args[argidx] == "-set_relaxed_checking") {
-				veri_file::SetRelaxedChecking(0);
+			if (args[argidx] == "-set_relaxed_file_ext_modes") {
+				veri_file::RemoveFileExt(".v");
+				veri_file::AddFileExtMode(".v", veri_file::SYSTEM_VERILOG);
+				veri_file::AddFileExtMode(".vh", veri_file::SYSTEM_VERILOG);
+				veri_file::AddFileExtMode(".sv", veri_file::SYSTEM_VERILOG);
+				veri_file::AddFileExtMode(".sv1", veri_file::SYSTEM_VERILOG);
+				veri_file::AddFileExtMode(".svh", veri_file::SYSTEM_VERILOG);
+				veri_file::AddFileExtMode(".svp", veri_file::SYSTEM_VERILOG);
+				veri_file::AddFileExtMode(".h", veri_file::SYSTEM_VERILOG);
+				veri_file::AddFileExtMode(".inc", veri_file::SYSTEM_VERILOG);
 				continue;
 			}
 #endif

From 4b166fb99bb2c6e11e1904b93146f26cf04a8255 Mon Sep 17 00:00:00 2001
From: Dhaval Chaudhari <dhavalchaudhari39@gmail.com>
Date: Sun, 4 Jan 2026 01:55:53 +0530
Subject: [PATCH 3/3] fix

---
 frontends/verific/verific.cc | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 20720872b..7a258c034 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -3688,23 +3688,23 @@ struct VerificPass : public Pass {
 				veri_file::AddLOption(args[++argidx].c_str());
 				continue;
 			}
-			if (args[argidx] == "-set_relaxed_file_ext_modes") {
-				veri_file::RemoveFileExt(".v");
-				veri_file::AddFileExtMode(".v", veri_file::SYSTEM_VERILOG);
-				veri_file::AddFileExtMode(".vh", veri_file::SYSTEM_VERILOG);
-				veri_file::AddFileExtMode(".sv", veri_file::SYSTEM_VERILOG);
-				veri_file::AddFileExtMode(".sv1", veri_file::SYSTEM_VERILOG);
-				veri_file::AddFileExtMode(".svh", veri_file::SYSTEM_VERILOG);
-				veri_file::AddFileExtMode(".svp", veri_file::SYSTEM_VERILOG);
-				veri_file::AddFileExtMode(".h", veri_file::SYSTEM_VERILOG);
-				veri_file::AddFileExtMode(".inc", veri_file::SYSTEM_VERILOG);
-				continue;
-			}
 #endif
 			break;
 		}
 
 #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
+		if (GetSize(args) > argidx && args[argidx] == "-set_relaxed_file_ext_modes") {
+			veri_file::RemoveFileExt(".v");
+			veri_file::AddFileExtMode(".v", veri_file::SYSTEM_VERILOG);
+			veri_file::AddFileExtMode(".vh", veri_file::SYSTEM_VERILOG);
+			veri_file::AddFileExtMode(".sv", veri_file::SYSTEM_VERILOG);
+			veri_file::AddFileExtMode(".sv1", veri_file::SYSTEM_VERILOG);
+			veri_file::AddFileExtMode(".svh", veri_file::SYSTEM_VERILOG);
+			veri_file::AddFileExtMode(".svp", veri_file::SYSTEM_VERILOG);
+			veri_file::AddFileExtMode(".h", veri_file::SYSTEM_VERILOG);
+			veri_file::AddFileExtMode(".inc", veri_file::SYSTEM_VERILOG);
+			continue;
+		}
 		if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
 		{
 			unsigned verilog_mode = veri_file::UNDEFINED;