mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-11 13:40:53 +00:00
Code Activity

CODEOWNERS: add myself for verilog frontend and ast layer

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-06-24 10:54:13 +02:00
parent 44aa313ba9
commit 7b2bf1fe2e
1 changed files with 2 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

5
CODEOWNERS
View file

@ -12,7 +12,9 @@
CODEOWNERS @nakengelhardt CODEOWNERS @nakengelhardt
passes/cmds/scratchpad.cc @nakengelhardt passes/cmds/scratchpad.cc @nakengelhardt
frontends/ast/ @widlarizer
frontends/rpc/ @whitequark frontends/rpc/ @whitequark
frontends/verilog/ @widlarizer
backends/cxxrtl/ @whitequark backends/cxxrtl/ @whitequark
passes/cmds/bugpoint.cc @whitequark passes/cmds/bugpoint.cc @whitequark
passes/techmap/flowmap.cc @whitequark passes/techmap/flowmap.cc @whitequark
@ -30,9 +32,6 @@ docs/source/using_yosys/synthesis/abc.rst @KrystalDelusion @Ravenslofty
# These still override previous lines, so be careful not to # These still override previous lines, so be careful not to
# accidentally disable any of the above rules. # accidentally disable any of the above rules.
frontends/verilog/ @zachjs
frontends/ast/ @zachjs
techlibs/intel_alm/ @Ravenslofty techlibs/intel_alm/ @Ravenslofty
techlibs/gowin/ @pepijndevos techlibs/gowin/ @pepijndevos
techlibs/gatemate/ @pu-cc techlibs/gatemate/ @pu-cc