mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
add support for memories to c++ and smtlib functional backends
This commit is contained in:
Emily Schmidt
parent
76371d177f
commit
7b29d177ac
5 changed files with 226 additions and 50 deletions
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@ -83,6 +83,41 @@ struct CxxScope {
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}
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};
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struct CxxType {
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bool _is_memory;
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int _width;
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int _addr_width;
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public:
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CxxType() : _is_memory(false), _width(0), _addr_width(0) { }
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CxxType(int width) : _is_memory(false), _width(width), _addr_width(0) { }
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CxxType(int addr_width, int data_width) : _is_memory(true), _width(data_width), _addr_width(addr_width) { }
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static CxxType signal(int width) { return CxxType(width); }
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static CxxType memory(int addr_width, int data_width) { return CxxType(addr_width, data_width); }
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bool is_signal() const { return !_is_memory; }
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bool is_memory() const { return _is_memory; }
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int width() const { log_assert(is_signal()); return _width; }
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int addr_width() const { log_assert(is_memory()); return _addr_width; }
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int data_width() const { log_assert(is_memory()); return _width; }
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std::string to_string() const {
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if(_is_memory) {
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return stringf("Memory<%d, %d>", addr_width(), data_width());
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} else {
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return stringf("Signal<%d>", width());
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}
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}
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bool operator ==(CxxType const& other) const {
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if(_is_memory != other._is_memory) return false;
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if(_is_memory && _addr_width != other._addr_width) return false;
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return _width == other._width;
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}
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unsigned int hash() const {
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if(_is_memory)
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return mkhash(1, mkhash(_width, _addr_width));
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else
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return mkhash(0, _width);
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}
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};
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struct CxxWriter {
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std::ostream &f;
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CxxWriter(std::ostream &out) : f(out) {}
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@ -97,7 +132,7 @@ struct CxxWriter {
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struct CxxStruct {
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std::string name;
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dict<IdString, std::string> types;
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dict<IdString, CxxType> types;
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CxxScope scope;
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bool generate_methods;
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int count;
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@ -106,14 +141,14 @@ struct CxxStruct {
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scope.reserve("out");
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scope.reserve("dump");
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}
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void insert(IdString name, std::string type) {
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void insert(IdString name, CxxType type) {
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scope.insert(name);
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types.insert({name, type});
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}
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void print(CxxWriter &f) {
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f.printf("struct %s {\n", name.c_str());
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for (auto p : types) {
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f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str());
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f.printf("\t%s %s;\n", p.second.to_string().c_str(), scope[p.first].c_str());
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}
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f.printf("\n\ttemplate <typename T> void dump(T &out) const {\n");
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for (auto p : types) {
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@ -149,7 +184,7 @@ struct CxxStruct {
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std::string generate_variant_types() const {
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std::set<std::string> unique_types;
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for (const auto& p : types) {
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unique_types.insert("std::reference_wrapper<" + p.second + ">");
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unique_types.insert("std::reference_wrapper<" + p.second.to_string() + ">");
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}
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std::ostringstream oss;
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for (auto it = unique_types.begin(); it != unique_types.end(); ++it) {
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@ -164,18 +199,18 @@ struct CxxStruct {
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struct CxxFunction {
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IdString name;
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int width;
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CxxType type;
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dict<IdString, Const> parameters;
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CxxFunction(IdString name, int width) : name(name), width(width) {}
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CxxFunction(IdString name, int width, dict<IdString, Const> parameters) : name(name), width(width), parameters(parameters) {}
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CxxFunction(IdString name, CxxType type) : name(name), type(type) {}
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CxxFunction(IdString name, CxxType type, dict<IdString, Const> parameters) : name(name), type(type), parameters(parameters) {}
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bool operator==(CxxFunction const &other) const {
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return name == other.name && parameters == other.parameters && width == other.width;
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return name == other.name && parameters == other.parameters && type == other.type;
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}
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unsigned int hash() const {
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return mkhash(name.hash(), parameters.hash());
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return mkhash(name.hash(), mkhash(type.hash(), parameters.hash()));
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}
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};
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@ -232,6 +267,9 @@ public:
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}
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T input(IdString name, int width) { return graph.add(CxxFunction(ID($$input), width, {{name, {}}}), 0); }
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T state(IdString name, int width) { return graph.add(CxxFunction(ID($$state), width, {{name, {}}}), 0); }
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T state_memory(IdString name, int addr_width, int data_width) {
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return graph.add(CxxFunction(ID($$state), CxxType::memory(addr_width, data_width), {{name, {}}}), 0);
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}
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T cell_output(T cell, IdString type, IdString name, int width) {
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if (is_single_output(type))
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return cell;
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@ -245,12 +283,19 @@ public:
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return graph.add(CxxFunction(ID($$undriven), width), 0);
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}
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T memory_read(T mem, T addr, int addr_width, int data_width) {
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return graph.add(CxxFunction(ID($memory_read), data_width), 0, std::array<T, 2>{mem, addr});
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}
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T memory_write(T mem, T addr, T data, int addr_width, int data_width) {
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return graph.add(CxxFunction(ID($memory_write), CxxType::memory(addr_width, data_width)), 0, std::array<T, 3>{mem, addr, data});
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}
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T create_pending(int width) {
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return graph.add(CxxFunction(ID($$pending), width), 0);
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}
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void update_pending(T pending, T node) {
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log_assert(pending.function().name == ID($$pending));
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pending.set_function(CxxFunction(ID($$buf), pending.function().width));
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pending.set_function(CxxFunction(ID($$buf), pending.function().type));
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pending.append_arg(node);
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}
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void declare_output(T node, IdString name, int) {
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@ -259,6 +304,9 @@ public:
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void declare_state(T node, IdString name, int) {
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node.assign_key(name);
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}
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void declare_state_memory(T node, IdString name, int, int) {
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node.assign_key(name);
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}
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void suggest_name(T node, IdString name) {
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node.sparse_attr() = name;
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}
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@ -312,8 +360,10 @@ struct FunctionalCxxBackend : public Backend
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{
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int target_index = alias[node.arg(0).index()];
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auto target_node = compute_graph[perm[target_index]];
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if(!target_node.has_sparse_attr() && node.has_sparse_attr())
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target_node.sparse_attr() = node.sparse_attr();
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if(!target_node.has_sparse_attr() && node.has_sparse_attr()){
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IdString id = node.sparse_attr();
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target_node.sparse_attr() = id;
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}
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alias.push_back(target_index);
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}
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else
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@ -328,7 +378,7 @@ struct FunctionalCxxBackend : public Backend
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void printCxx(std::ostream &stream, std::string, std::string const & name, CxxComputeGraph &compute_graph)
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{
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dict<IdString, int> inputs, state;
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dict<IdString, CxxType> inputs, state;
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CxxWriter f(stream);
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// Dump the compute graph
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@ -336,22 +386,22 @@ struct FunctionalCxxBackend : public Backend
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{
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auto ref = compute_graph[i];
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if(ref.function().name == ID($$input))
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inputs[ref.function().parameters.begin()->first] = ref.function().width;
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inputs[ref.function().parameters.begin()->first] = ref.function().type;
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if(ref.function().name == ID($$state))
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state[ref.function().parameters.begin()->first] = ref.function().width;
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state[ref.function().parameters.begin()->first] = ref.function().type;
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}
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f.printf("#include \"sim.h\"\n");
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f.printf("#include <variant>\n");
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CxxStruct input_struct(name + "_Inputs", true, inputs.size());
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for (auto const &input : inputs)
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input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">");
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input_struct.insert(input.first, input.second);
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CxxStruct output_struct(name + "_Outputs");
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for (auto const &key : compute_graph.keys())
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if(state.count(key.first) == 0)
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output_struct.insert(key.first, "Signal<" + std::to_string(compute_graph[key.second].function().width) + ">");
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output_struct.insert(key.first, compute_graph[key.second].function().type);
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CxxStruct state_struct(name + "_State");
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for (auto const &state_var : state)
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state_struct.insert(state_var.first, "Signal<" + std::to_string(state_var.second) + ">");
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state_struct.insert(state_var.first, state_var.second);
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idict<std::string> node_names;
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CxxScope locals;
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@ -368,7 +418,7 @@ struct FunctionalCxxBackend : public Backend
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for (int i = 0; i < compute_graph.size(); ++i)
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{
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auto ref = compute_graph[i];
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int width = ref.function().width;
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auto type = ref.function().type;
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std::string name;
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if(ref.has_sparse_attr())
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name = locals.insert(ref.sparse_attr());
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@ -376,19 +426,19 @@ struct FunctionalCxxBackend : public Backend
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name = locals.insert("\\n" + std::to_string(i));
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node_names(name);
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if(ref.function().name == ID($$input))
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f.printf("\tSignal<%d> %s = input.%s;\n", width, name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str());
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f.printf("\t%s %s = input.%s;\n", type.to_string().c_str(), name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str());
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else if(ref.function().name == ID($$state))
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f.printf("\tSignal<%d> %s = current_state.%s;\n", width, name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str());
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f.printf("\t%s %s = current_state.%s;\n", type.to_string().c_str(), name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str());
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else if(ref.function().name == ID($$buf))
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f.printf("\tSignal<%d> %s = %s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str());
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f.printf("\t%s %s = %s;\n", type.to_string().c_str(), name.c_str(), node_names[ref.arg(0).index()].c_str());
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else if(ref.function().name == ID($$cell_output))
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f.printf("\tSignal<%d> %s = %s.%s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str());
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f.printf("\t%s %s = %s.%s;\n", type.to_string().c_str(), name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str());
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else if(ref.function().name == ID($$const)){
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auto c = ref.function().parameters.begin()->second;
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if(c.size() <= 32){
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f.printf("\tSignal<%d> %s = $const<%d>(%#x);\n", width, name.c_str(), width, (uint32_t) c.as_int());
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f.printf("\t%s %s = $const<%d>(%#x);\n", type.to_string().c_str(), name.c_str(), type.width(), (uint32_t) c.as_int());
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}else{
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f.printf("\tSignal<%d> %s = $const<%d>({%#x", width, name.c_str(), width, (uint32_t) c.as_int());
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f.printf("\t%s %s = $const<%d>({%#x", type.to_string().c_str(), name.c_str(), type.width(), (uint32_t) c.as_int());
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while(c.size() > 32){
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c = c.extract(32, c.size() - 32);
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f.printf(", %#x", c.as_int());
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@ -396,9 +446,9 @@ struct FunctionalCxxBackend : public Backend
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f.printf("});\n");
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}
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}else if(ref.function().name == ID($$undriven))
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f.printf("\tSignal<%d> %s; //undriven\n", width, name.c_str());
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f.printf("\t%s %s; //undriven\n", type.to_string().c_str(), name.c_str());
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else if(ref.function().name == ID($$slice))
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f.printf("\tSignal<%d> %s = slice<%d>(%s, %d);\n", width, name.c_str(), width, node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int());
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f.printf("\t%s %s = slice<%d>(%s, %d);\n", type.to_string().c_str(), name.c_str(), type.width(), node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int());
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else if(ref.function().name == ID($$concat)){
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f.printf("\tauto %s = concat(", name.c_str());
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for (int i = 0, end = ref.size(); i != end; ++i){
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@ -409,11 +459,7 @@ struct FunctionalCxxBackend : public Backend
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f.printf(");\n");
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}else{
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f.printf("\t");
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if(ref.function().width > 0)
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f.printf("Signal<%d>", ref.function().width);
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else
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f.printf("%s_Outputs", log_id(ref.function().name));
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f.printf(" %s = %s", name.c_str(), log_id(ref.function().name));
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f.printf("%s %s = %s", type.to_string().c_str(), name.c_str(), log_id(ref.function().name));
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if(ref.function().parameters.count(ID(WIDTH))){
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f.printf("<%d>", ref.function().parameters.at(ID(WIDTH)).as_int());
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}
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@ -363,4 +363,23 @@ Signal<n> $sign_extend(Signal<m> const& a)
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return ret;
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}
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template<size_t a, size_t d>
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struct Memory {
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std::array<Signal<d>, 1<<a> contents;
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};
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template<size_t a, size_t d>
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Signal<d> $memory_read(Memory<a, d> memory, Signal<a> addr)
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{
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return memory.contents[as_int(addr)];
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}
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template<size_t a, size_t d>
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Memory<a, d> $memory_write(Memory<a, d> memory, Signal<a> addr, Signal<d> data)
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{
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Memory<a, d> ret = memory;
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ret.contents[as_int(addr)] = data;
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return ret;
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}
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#endif
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@ -219,19 +219,54 @@ std::ostream& operator << (std::ostream &os, SExpr const &s) {
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return os;
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}
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struct SmtlibType {
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bool _is_memory;
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int _width;
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int _addr_width;
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public:
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SmtlibType() : _is_memory(false), _width(0), _addr_width(0) { }
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SmtlibType(int width) : _is_memory(false), _width(width), _addr_width(0) { }
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SmtlibType(int addr_width, int data_width) : _is_memory(true), _width(data_width), _addr_width(addr_width) { }
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static SmtlibType signal(int width) { return SmtlibType(width); }
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static SmtlibType memory(int addr_width, int data_width) { return SmtlibType(addr_width, data_width); }
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bool is_signal() const { return !_is_memory; }
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bool is_memory() const { return _is_memory; }
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int width() const { log_assert(is_signal()); return _width; }
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int addr_width() const { log_assert(is_memory()); return _addr_width; }
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int data_width() const { log_assert(is_memory()); return _width; }
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SExpr to_sexpr() const {
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if(_is_memory) {
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return SExpr{ "Array", SExpr{ "_", "BitVec", addr_width() }, SExpr{ "_", "BitVec", data_width() }};
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} else {
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return SExpr{ "_", "BitVec", width() };
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}
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}
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bool operator ==(SmtlibType const& other) const {
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if(_is_memory != other._is_memory) return false;
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if(_is_memory && _addr_width != other._addr_width) return false;
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return _width == other._width;
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}
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unsigned int hash() const {
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if(_is_memory)
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return mkhash(1, mkhash(_width, _addr_width));
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else
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return mkhash(0, _width);
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}
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};
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struct SmtlibStruct {
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SmtlibScope &scope;
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std::string name;
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idict<IdString> members;
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vector<int> widths;
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vector<SmtlibType> types;
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vector<std::string> accessors;
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SmtlibStruct(std::string name, SmtlibScope &scope) : scope(scope), name(name) {
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}
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std::string insert(IdString field, int width) {
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std::string insert(IdString field, SmtlibType type) {
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if(members.at(field, -1) == -1){
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members(field);
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scope.insert(field);
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widths.push_back(width);
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types.push_back(type);
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accessors.push_back(scope.insert(std::string("\\") + name + "_" + RTLIL::unescape_id(field)));
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}
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return scope[field];
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@ -239,7 +274,7 @@ struct SmtlibStruct {
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void print(SmtlibWriter &f) {
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f.printf("(declare-datatype %s ((%s\n", name.c_str(), name.c_str());
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for (size_t i = 0; i < members.size(); i++)
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f.printf(" (%s (_ BitVec %d))\n", accessors[i].c_str(), widths[i]);
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f << " " << SExpr{accessors[i], types[i].to_sexpr()} << "\n";
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f.printf(")))\n");
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}
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void print_value(SmtlibWriter &f, dict<IdString, SExpr> values, int indentation) {
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@ -260,16 +295,16 @@ struct SmtlibStruct {
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struct Node {
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SExpr expr;
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int width;
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SmtlibType type;
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Node(SExpr &&expr, int width) : expr(std::move(expr)), width(width) {}
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Node(SExpr &&expr, SmtlibType type) : expr(std::move(expr)), type(type) {}
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bool operator==(Node const &other) const {
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return expr == other.expr && width == other.width;
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return expr == other.expr && type == other.type;
|
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}
|
||||
|
||||
unsigned int hash() const {
|
||||
return mkhash(expr.hash(), width);
|
||||
return mkhash(expr.hash(), type.hash());
|
||||
}
|
||||
};
|
||||
|
||||
|
|
@ -302,8 +337,8 @@ class SmtlibComputeGraphFactory {
|
|||
auto it = yosys_celltypes.cell_types.find(type);
|
||||
return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1;
|
||||
}
|
||||
T node(SExpr &&expr, int width, std::initializer_list<T> args) {
|
||||
return graph.add(Node(std::move(expr), width), 0, args);
|
||||
T node(SExpr &&expr, SmtlibType type, std::initializer_list<T> args) {
|
||||
return graph.add(Node(std::move(expr), type), 0, args);
|
||||
}
|
||||
T shift(const char *name, T a, T b, int y_width, int b_width, bool a_signed = false) {
|
||||
int width = max(y_width, b_width);
|
||||
|
|
@ -367,6 +402,13 @@ public:
|
|||
T logical_shift_right(T a, T b, int y_width, int b_width) { return shift("bvlshl", a, b, y_width, b_width); }
|
||||
T arithmetic_shift_right(T a, T b, int y_width, int b_width) { return shift("bvashr", a, b, y_width, b_width, true); }
|
||||
|
||||
T memory_read(T mem, T addr, int addr_width, int data_width) {
|
||||
return node(SExpr {"select", Arg(1), Arg(2)}, data_width, {mem, addr});
|
||||
}
|
||||
T memory_write(T mem, T addr, T data, int addr_width, int data_width) {
|
||||
return node(SExpr {"store", Arg(1), Arg(2), Arg(3)}, SmtlibType::memory(addr_width, data_width), {mem, addr, data});
|
||||
}
|
||||
|
||||
T constant(RTLIL::Const value) { return node(SExpr(value), value.size(), {}); }
|
||||
T input(IdString name, int width) {
|
||||
module.input_struct.insert(name, width);
|
||||
|
|
@ -376,6 +418,10 @@ public:
|
|||
module.state_struct.insert(name, width);
|
||||
return node(module.state_struct.access("current_state", name), width, {});
|
||||
}
|
||||
T state_memory(IdString name, int addr_width, int data_width) {
|
||||
module.state_struct.insert(name, SmtlibType::memory(addr_width, data_width));
|
||||
return node(module.state_struct.access("current_state", name), SmtlibType::memory(addr_width, data_width), {});
|
||||
}
|
||||
T cell_output(T cell, IdString type, IdString name, int width) {
|
||||
if (is_single_output(type))
|
||||
return cell;
|
||||
|
|
@ -399,7 +445,7 @@ public:
|
|||
}
|
||||
void update_pending(T pending, T node) {
|
||||
log_assert(pending.function().expr.is_none());
|
||||
pending.set_function(Node(Arg(1), pending.function().width));
|
||||
pending.set_function(Node(Arg(1), pending.function().type));
|
||||
pending.append_arg(node);
|
||||
}
|
||||
void declare_output(T node, IdString name, int width) {
|
||||
|
|
@ -410,6 +456,10 @@ public:
|
|||
module.state_struct.insert(name, width);
|
||||
node.assign_key(name);
|
||||
}
|
||||
void declare_state_memory(T node, IdString name, int addr_width, int data_width) {
|
||||
module.state_struct.insert(name, SmtlibType::memory(addr_width, data_width));
|
||||
node.assign_key(name);
|
||||
}
|
||||
void suggest_name(T node, IdString name) {
|
||||
node.sparse_attr() = name;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1064,6 +1064,13 @@ public:
|
|||
append(bit);
|
||||
}
|
||||
|
||||
DriveSpec(SigSpec const &sig)
|
||||
{
|
||||
// TODO: converting one chunk at a time would be faster
|
||||
for (auto const &bit : sig.bits())
|
||||
append(bit);
|
||||
}
|
||||
|
||||
std::vector<DriveChunk> const &chunks() const { pack(); return chunks_; }
|
||||
std::vector<DriveBit> const &bits() const { unpack(); return bits_; }
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include "kernel/yosys.h"
|
||||
#include "kernel/drivertools.h"
|
||||
#include "kernel/functional.h"
|
||||
#include "kernel/mem.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
|
@ -71,6 +72,11 @@ public:
|
|||
T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width);
|
||||
return factory.arithmetic_shift_right(a, reduced_b, y_width, reduced_b_width);
|
||||
}
|
||||
T bitwise_mux(T a, T b, T s, int width) {
|
||||
T aa = factory.bitwise_and(a, factory.bitwise_not(s, width), width);
|
||||
T bb = factory.bitwise_and(b, s, width);
|
||||
return factory.bitwise_or(aa, bb, width);
|
||||
}
|
||||
CellSimplifier(Factory &f) : factory(f) {}
|
||||
T handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, T> inputs)
|
||||
{
|
||||
|
|
@ -104,7 +110,7 @@ public:
|
|||
T b = extend(inputs.at(ID(B)), b_width, width, is_signed);
|
||||
if(cellType.in({ID($eq), ID($eqx)}))
|
||||
return extend(factory.eq(a, b, width), 1, y_width, false);
|
||||
if(cellType.in({ID($ne), ID($nex)}))
|
||||
else if(cellType.in({ID($ne), ID($nex)}))
|
||||
return extend(factory.ne(a, b, width), 1, y_width, false);
|
||||
else if(cellType == ID($lt))
|
||||
return extend(is_signed ? factory.gt(b, a, width) : factory.ugt(b, a, width), 1, y_width, false);
|
||||
|
|
@ -197,6 +203,8 @@ class ComputeGraphConstruction {
|
|||
DriverMap driver_map;
|
||||
Factory& factory;
|
||||
CellSimplifier<T, Factory> simplifier;
|
||||
vector<Mem> memories_vector;
|
||||
dict<Cell*, Mem*> memories;
|
||||
|
||||
T enqueue(DriveSpec const &spec)
|
||||
{
|
||||
|
|
@ -224,6 +232,45 @@ public:
|
|||
factory.declare_output(node, wire->name, wire->width);
|
||||
}
|
||||
}
|
||||
memories_vector = Mem::get_all_memories(module);
|
||||
for (auto &mem : memories_vector) {
|
||||
if (mem.cell != nullptr)
|
||||
memories[mem.cell] = &mem;
|
||||
}
|
||||
}
|
||||
T concatenate_read_results(Mem *mem, vector<T> results)
|
||||
{
|
||||
if(results.size() == 0)
|
||||
return factory.undriven(0);
|
||||
T node = results[0];
|
||||
int size = results[0].size();
|
||||
for(size_t i = 1; i < results.size(); i++) {
|
||||
node = factory.concat(node, size, results[i], results[i].size());
|
||||
size += results[i].size();
|
||||
}
|
||||
return node;
|
||||
}
|
||||
T handle_memory(Mem *mem)
|
||||
{
|
||||
vector<T> read_results;
|
||||
int addr_width = ceil_log2(mem->size);
|
||||
int data_width = mem->width;
|
||||
T node = factory.state_memory(mem->cell->name, addr_width, data_width);
|
||||
for (auto &rd : mem->rd_ports) {
|
||||
log_assert(!rd.clk_enable);
|
||||
T addr = enqueue(driver_map(DriveSpec(rd.addr)));
|
||||
read_results.push_back(factory.memory_read(node, addr, addr_width, data_width));
|
||||
}
|
||||
for (auto &wr : mem->wr_ports) {
|
||||
T en = enqueue(driver_map(DriveSpec(wr.en)));
|
||||
T addr = enqueue(driver_map(DriveSpec(wr.addr)));
|
||||
T new_data = enqueue(driver_map(DriveSpec(wr.data)));
|
||||
T old_data = factory.memory_read(node, addr, addr_width, data_width);
|
||||
T wr_data = simplifier.bitwise_mux(old_data, new_data, en, data_width);
|
||||
node = factory.memory_write(node, addr, wr_data, addr_width, data_width);
|
||||
}
|
||||
factory.declare_state_memory(node, mem->cell->name, addr_width, data_width);
|
||||
return concatenate_read_results(mem, read_results);
|
||||
}
|
||||
void process_queue()
|
||||
{
|
||||
|
|
@ -306,6 +353,12 @@ public:
|
|||
factory.update_pending(pending, node);
|
||||
} else if (chunk.is_marker()) {
|
||||
Cell *cell = cells[chunk.marker().marker];
|
||||
if (cell->is_mem_cell()) {
|
||||
Mem *mem = memories.at(cell, nullptr);
|
||||
log_assert(mem != nullptr);
|
||||
T node = handle_memory(mem);
|
||||
factory.update_pending(pending, node);
|
||||
} else {
|
||||
dict<IdString, T> connections;
|
||||
for(auto const &conn : cell->connections()) {
|
||||
if(driver_map.celltypes.cell_input(cell->type, conn.first))
|
||||
|
|
@ -313,6 +366,7 @@ public:
|
|||
}
|
||||
T node = simplifier.handle(cell->type, cell->parameters, connections);
|
||||
factory.update_pending(pending, node);
|
||||
}
|
||||
} else if (chunk.is_none()) {
|
||||
T node = factory.undriven(chunk.size());
|
||||
factory.update_pending(pending, node);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue