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Move ABC FF stuff to abc_ff.v; add support for other FD* types

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Eddie Hung 2019-07-10 17:06:05 -07:00
parent 0ab8f28bc7
commit 7b2599cb94
4 changed files with 135 additions and 27 deletions
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114
techlibs/xilinx/abc_ff.v
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@ -20,14 +20,124 @@
// ============================================================================
module FDRE (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
wire \$nextQ ;
\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R));
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
endmodule
module FDRE_1 (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
wire \$nextQ ;
\$__ABC_FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R));
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
endmodule
module FDCE (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
wire \$nextQ , \$currQ ;
\$__ABC_FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
\$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
endmodule
module FDCE_1 (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
wire \$nextQ , \$currQ ;
\$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
\$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
endmodule
module FDPE (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
wire \$nextQ , \$currQ ;
\$__ABC_FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE));
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
generate
if (IS_PRE_INVERTED)
\$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
else
\$__ABC_MUX_ abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q));
endgenerate
endmodule
module FDPE_1 (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
wire \$nextQ , \$currQ ;
\$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE));
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
\$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
endmodule
`ifndef _ABC
module \$__ABC_FF_ (input C, D, output Q);
endmodule
(* abc_box_id = 8, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
(* abc_box_id = 1000 *)
module \$__ABC_FD_ASYNC_MUX_ (input A, B, S, output Q);
// assign Q = S ? B : A;
endmodule
(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
endmodule
(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1,D,Q,\\$pastQ" *)
module \$__ABC_FDRE_1 (output Q, input C, CE, D, R, \$pastQ );
parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
endmodule
(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE,D,Q,\\$pastQ" *)
module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
//parameter [0:0] IS_CLR_INVERTED = 1'b0;
assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule
(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *)
module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
//parameter [0:0] IS_CLR_INVERTED = 1'b0;
assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule
(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *)
module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
//parameter [0:0] IS_PRE_INVERTED = 1'b0;
assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule
(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *)
module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
//parameter [0:0] IS_PRE_INVERTED = 1'b0;
assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule
`endif