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ice40, ecp5, gowin: enable ABC9 by default

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This commit is contained in:
Lofty 2023-11-13 15:12:23 +00:00
parent 5691cd0958
commit 7ae4041e20
10 changed files with 46 additions and 22 deletions
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3
tests/arch/gowin/counter.ys
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@ -6,10 +6,11 @@ equiv_opt -assert -multiclock -map +/gowin/cells_sim.v synth_gowin # equivalency
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT1
select -assert-count 8 t:DFFC
select -assert-count 8 t:ALU
select -assert-count 1 t:GND
select -assert-count 1 t:VCC
select -assert-count 2 t:IBUF
select -assert-count 8 t:OBUF
select -assert-none t:DFFC t:ALU t:GND t:VCC t:IBUF t:OBUF %% t:* %D
select -assert-none t:LUT1 t:DFFC t:ALU t:GND t:VCC t:IBUF t:OBUF %% t:* %D

2
tests/arch/gowin/init.ys
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@ -1,5 +1,5 @@
read_verilog init.v
read_verilog -lib +/gowin/cells_sim.v
read_verilog -lib -specify +/gowin/cells_sim.v
design -save read
proc

9
tests/arch/gowin/mux.ys
View file

@ -32,10 +32,17 @@ proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT1
select -assert-count 10 t:LUT3
select -assert-count 1 t:LUT4
select -assert-count 5 t:MUX2_LUT5
select -assert-count 2 t:MUX2_LUT6
select -assert-count 1 t:MUX2_LUT7
select -assert-count 11 t:IBUF
select -assert-count 1 t:OBUF
select -assert-count 1 t:GND
select -assert-none t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
select -assert-none t:LUT* t:MUX2_LUT7 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF t:GND %% t:* %D
design -load read
hierarchy -top mux16