3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00

kernel: share a single CellTypes within a pass

This commit is contained in:
Eddie Hung 2020-03-18 12:21:40 -07:00
parent a0cc795e85
commit 7ad7f41bc5
4 changed files with 51 additions and 31 deletions

View file

@ -31,9 +31,8 @@ PRIVATE_NAMESPACE_BEGIN
bool did_something;
void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
void replace_undriven(RTLIL::Module *module, const CellTypes& ct)
{
CellTypes ct(design);
SigMap sigmap(module);
SigPool driven_signals;
SigPool used_signals;
@ -1737,13 +1736,14 @@ struct OptExprPass : public Pass {
}
extra_args(args, argidx, design);
CellTypes ct(design);
for (auto module : design->selected_modules())
{
log("Optimizing module %s.\n", log_id(module));
if (undriven) {
did_something = false;
replace_undriven(design, module);
replace_undriven(module, ct);
if (did_something)
design->scratchpad_set_bool("opt.did_something", true);
}