mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-06 03:10:26 +00:00
Code Activity

kernel: share a single CellTypes within a pass

Browse source
This commit is contained in:
Eddie Hung 2020-03-18 12:21:40 -07:00
parent a0cc795e85
commit 7ad7f41bc5
4 changed files with 51 additions and 31 deletions
Download patch file Download diff file Expand all files Collapse all files

20
passes/memory/memory_share.cc
View file

@ -665,9 +665,18 @@ struct MemoryShareWorker
// Setup and run
// -------------
MemoryShareWorker(RTLIL::Design *design, RTLIL::Module *module) :
design(design), module(module), sigmap(module)
MemoryShareWorker(RTLIL::Design *design) :
design(design), modwalker(design)
{
}
void operator()(RTLIL::Module* module)
{
this->module = module;
sigmap.set(module);
sig_to_mux.clear();
conditions_logic_cache.clear();
std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
sigmap_xmux = sigmap;
@ -717,7 +726,7 @@ struct MemoryShareWorker
cone_ct.cell_types.erase("$shift");
cone_ct.cell_types.erase("$shiftx");
modwalker.setup(design, module, &cone_ct);
modwalker.setup(module, &cone_ct);
for (auto &it : memindex)
consolidate_wr_using_sat(it.first, it.second.second);
@ -755,8 +764,11 @@ struct MemorySharePass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n");
extra_args(args, 1, design);
MemoryShareWorker msw(design);
for (auto module : design->selected_modules())
MemoryShareWorker(design, module);
msw(module);
}
} MemorySharePass;