3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00

kernel: share a single CellTypes within a pass

This commit is contained in:
Eddie Hung 2020-03-18 12:21:40 -07:00
parent a0cc795e85
commit 7ad7f41bc5
4 changed files with 51 additions and 31 deletions

View file

@ -380,22 +380,15 @@ struct ModWalker
}
}
ModWalker() : design(NULL), module(NULL)
ModWalker(RTLIL::Design *design) : design(design), module(NULL)
{
ct.setup(design);
}
ModWalker(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL)
void setup(RTLIL::Module *module, CellTypes *filter_ct = NULL)
{
setup(design, module, filter_ct);
}
void setup(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL)
{
this->design = design;
this->module = module;
ct.clear();
ct.setup(design);
sigmap.set(module);
signal_drivers.clear();