mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Add -suffix option to rename -wire.

Browse source 
See #3195
This commit is contained in:
bfg86 2022-02-11 00:05:13 +01:00
parent 61324cf55f
commit 7ac98d1c87
1 changed files with 13 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

17
passes/cmds/rename.cc
View file

@ -66,7 +66,7 @@ static std::string derive_name_from_src(const std::string &src, int counter)
return stringf("\\%s$%d", src_base.c_str(), counter); return stringf("\\%s$%d", src_base.c_str(), counter);
} }
static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell) static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell, string suffix)
{ {
// Find output // Find output
const SigSpec *output = nullptr; const SigSpec *output = nullptr;
@ -99,7 +99,10 @@ static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell)
} }
} }
return name + cell->type.str(); if (suffix.empty()) {
suffix = cell->type.str();
}
return name + suffix;
} }
struct RenamePass : public Pass { struct RenamePass : public Pass {
@ -127,10 +130,12 @@ struct RenamePass : public Pass {
log("cells with private names.\n"); log("cells with private names.\n");
log("\n"); log("\n");
log("\n"); log("\n");
log(" rename -wire [selection]\n"); log(" rename -wire [selection] [-suffix <suffix>]\n");
log("\n"); log("\n");
log("Assign auto-generated names based on the wires they drive to all selected\n"); log("Assign auto-generated names based on the wires they drive to all selected\n");
log("cells with private names. Ignores cells driving privatly named wires.\n"); log("cells with private names. Ignores cells driving privatly named wires.\n");
log("The -suffix option can be used to set a suffix to the renamed cells.\n");
log("The default suffix is the cell type.\n");
log("\n"); log("\n");
log("\n"); log("\n");
log(" rename -enumerate [-pattern <pattern>] [selection]\n"); log(" rename -enumerate [-pattern <pattern>] [selection]\n");
@ -155,6 +160,7 @@ struct RenamePass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
std::string pattern_prefix = "_", pattern_suffix = "_"; std::string pattern_prefix = "_", pattern_suffix = "_";
std::string cell_suffix = "";
bool flag_src = false; bool flag_src = false;
bool flag_wire = false; bool flag_wire = false;
bool flag_enumerate = false; bool flag_enumerate = false;
@ -203,6 +209,9 @@ struct RenamePass : public Pass {
pattern_suffix = args[argidx].substr(pos+1); pattern_suffix = args[argidx].substr(pos+1);
continue; continue;
} }
if (arg == "-suffix" && argidx + 1 < args.size()) {
cell_suffix = args[++argidx];
}
break; break;
} }
@ -240,7 +249,7 @@ struct RenamePass : public Pass {
dict<RTLIL::Cell *, IdString> new_cell_names; dict<RTLIL::Cell *, IdString> new_cell_names;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
if (cell->name[0] == '$') if (cell->name[0] == '$')
new_cell_names[cell] = derive_name_from_cell_output_wire(cell); new_cell_names[cell] = derive_name_from_cell_output_wire(cell, cell_suffix);
for (auto &it : new_cell_names) for (auto &it : new_cell_names)
module->rename(it.first, it.second); module->rename(it.first, it.second);
} }