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Add memory rules for RAM16X1D, RAM32M, RAM64M

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This commit is contained in:
Eddie Hung 2019-12-12 17:44:59 -08:00
parent caab66111e
commit 7a9d1be97d
2 changed files with 168 additions and 0 deletions
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64
techlibs/xilinx/lutrams.txt
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@ -1,4 +1,17 @@
bram $__XILINX_RAM16X1D
init 1
abits 4
dbits 1
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
bram $__XILINX_RAM32X1D
init 1
abits 5
@ -38,6 +51,41 @@ bram $__XILINX_RAM128X1D
clkpol 0 2
endbram
bram $__XILINX_RAM32M
init 1
abits 5
dbits 2
groups 2
ports 3 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
bram $__XILINX_RAM64M
init 1
abits 6
dbits 1
groups 2
ports 3 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
match $__XILINX_RAM16X1D
min bits 2
min wports 1
make_outreg
or_next_if_better
endmatch
match $__XILINX_RAM32X1D
min bits 3
min wports 1
@ -56,5 +104,21 @@ match $__XILINX_RAM128X1D
min bits 9
min wports 1
make_outreg
or_next_if_better
endmatch
match $__XILINX_RAM32M
min bits 5
min rports 3
min wports 1
make_outreg
or_next_if_better
endmatch
match $__XILINX_RAM64M
min bits 5
min rports 3
min wports 1
make_outreg
endmatch