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Improvements and bugfixes for generate blocks with local signals

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This commit is contained in:
Clifford Wolf 2013-03-26 11:13:58 +01:00
parent 6a382f2aba
commit 7a99349de4
2 changed files with 2 additions and 4 deletions
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4
frontends/ast/simplify.cc
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@ -896,10 +896,8 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma
return; return;
} }
if ((type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL) && name_map.count(str) > 0) { if ((type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL) && name_map.count(str) > 0)
str = name_map[str]; str = name_map[str];
return;
}
std::map<std::string, std::string> backup_name_map; std::map<std::string, std::string> backup_name_map;

2
frontends/verilog/lexer.l
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@ -184,7 +184,7 @@ supply1 { return TOK_SUPPLY1; }
"$signed" { return TOK_TO_SIGNED; } "$signed" { return TOK_TO_SIGNED; }
"$unsigned" { return TOK_TO_UNSIGNED; } "$unsigned" { return TOK_TO_UNSIGNED; }
[a-zA-Z_$][a-zA-Z0-9_$]* { [a-zA-Z_$][a-zA-Z0-9_\.$]* {
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
return TOK_ID; return TOK_ID;
} }