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Improvements and bugfixes for generate blocks with local signals

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This commit is contained in:
Clifford Wolf 2013-03-26 11:13:58 +01:00
parent 6a382f2aba
commit 7a99349de4
2 changed files with 2 additions and 4 deletions
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2
frontends/verilog/lexer.l
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@ -184,7 +184,7 @@ supply1 { return TOK_SUPPLY1; }
"$signed" { return TOK_TO_SIGNED; }
"$unsigned" { return TOK_TO_UNSIGNED; }
[a-zA-Z_$][a-zA-Z0-9_$]* {
[a-zA-Z_$][a-zA-Z0-9_\.$]* {
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
return TOK_ID;
}